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AJvYcCX1YYmO66lOqZnHi8mRPDqkq19fXZ125gkdGE4/D8C8idVEwdrJ4cPNjzZ4X86kBHBsvFLnPCdoD3sc42Q=@vger.kernel.org X-Gm-Message-State: AOJu0YzzuZhI7eTHX3wxkmlBtsawGt/ACSQpUSnDRyIky6EDGdvCWtBC 6cisr2ZVc5+cjWjQjRHNw/mj4WxsAACAmH/PYQscAMyAWG8xGV5bBvh4hyowWR8= X-Google-Smtp-Source: AGHT+IE+VqIT7vTmF8ezn+F1ZGxsArBTbxlssPG2IpR2sbFySryxvu3aXD+F6VGAslKGkRyTzyn/DA== X-Received: by 2002:a05:6870:82a1:b0:270:735:96e with SMTP id 586e51a60fabf-273e6465ed4mr12975071fac.12.1724707029195; Mon, 26 Aug 2024 14:17:09 -0700 (PDT) Received: from [192.168.86.42] ([136.62.208.201]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-273ce99851fsm2666949fac.10.2024.08.26.14.17.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Aug 2024 14:17:08 -0700 (PDT) Message-ID: <6fa4f5e5-7f7b-495a-a95a-82d7b105d2d7@utexas.edu> Date: Mon, 26 Aug 2024 16:17:07 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] arm64: dts: ti: k3-am64* Disable ethernet by default at SoC level To: Daniel Schultz Cc: Josua Mayer , Wadim Egorov , linux@ew.tq-group.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Conor Dooley , Krzysztof Kozlowski , Vignesh Raghavendra , Nishanth Menon References: <20240809135753.1186-1-logan.bristol@utexas.edu> <4e884c6c-ec82-4229-a2a4-55da66cc284f@phytec.de> Content-Language: en-US From: Logan Bristol In-Reply-To: <4e884c6c-ec82-4229-a2a4-55da66cc284f@phytec.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Daniel, On 8/26/2024 12:29 AM, Daniel Schultz wrote: > Hey Logan, > > my feedback is similar to Josua's. > > On 09.08.24 15:57, Logan Bristol wrote: >> External interfaces should be disabled at the SoC DTSI level, since >> the node is incomplete. Disable Ethernet switch and ports in SoC DTSI >> and enable them in the board DTS. If the board DTS includes a SoM DTSI >> that completes the node description, enable the Ethernet switch and ports >> in SoM DTSI. >> >> Reflect this change in SoM DTSIs by removing ethernet port disable. >> >> Signed-off-by: Logan Bristol >> --- >> Changes since v1: >> - Enabled cpsw3g and cpsw_port1 in SoM DTSI instead of board DTS >> if board DTS included SoM DTSI >> --- >>   arch/arm64/boot/dts/ti/k3-am64-main.dtsi               | 3 +++ >>   arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi        | 6 ++---- >>   arch/arm64/boot/dts/ti/k3-am642-evm.dts                | 3 +++ >>   arch/arm64/boot/dts/ti/k3-am642-sk.dts                 | 3 +++ >>   arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi            | 6 ++---- >>   arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 6 ++---- >>   6 files changed, 15 insertions(+), 12 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/ >> boot/dts/ti/k3-am64-main.dtsi >> index f8370dd03350..69c5af58b727 100644 >> --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi >> @@ -677,6 +677,7 @@ cpsw3g: ethernet@8000000 { >>           assigned-clock-parents = <&k3_clks 13 9>; >>           clock-names = "fck"; >>           power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; >> +        status = "disabled"; >>           dmas = <&main_pktdma 0xC500 15>, >>                  <&main_pktdma 0xC501 15>, >> @@ -701,6 +702,7 @@ cpsw_port1: port@1 { >>                   phys = <&phy_gmii_sel 1>; >>                   mac-address = [00 00 00 00 00 00]; >>                   ti,syscon-efuse = <&main_conf 0x200>; >> +                status = "disabled"; >>               }; >>               cpsw_port2: port@2 { >> @@ -709,6 +711,7 @@ cpsw_port2: port@2 { >>                   label = "port2"; >>                   phys = <&phy_gmii_sel 2>; >>                   mac-address = [00 00 00 00 00 00]; >> +                status = "disabled"; >>               }; >>           }; >> diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/ >> arm64/boot/dts/ti/k3-am64-phycore-som.dtsi >> index ea7c58fb67e2..6bece2fb4e95 100644 >> --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi >> @@ -185,6 +185,7 @@ AM64X_IOPAD(0x0278, PIN_INPUT, 7)    /* (C19) >> EXTINTn.GPIO1_70 */ >>   &cpsw3g { >>       pinctrl-names = "default"; >>       pinctrl-0 = <&cpsw_rgmii1_pins_default>; >> +    status = "okay"; >>   }; >>   &cpsw3g_mdio { >> @@ -208,10 +209,7 @@ cpsw3g_phy1: ethernet-phy@1 { >>   &cpsw_port1 { >>       phy-mode = "rgmii-rxid"; >>       phy-handle = <&cpsw3g_phy1>; > The connected phy is located on the SOM and should be enabled by default. >> -}; >> - >> -&cpsw_port2 { >> -    status = "disabled"; >> +    status = "okay"; >>   }; > > This port is routed to the carrier-board. Please drop this node. I replied similarly to Josua's comments, but if cpsw_port1 is to be enabled and cpsw_port2 should be dropped from this DTSI, isn't that shown in this diff? Thank you, Logan Bristol