From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58D4F2F6175 for ; Wed, 22 Oct 2025 07:24:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761117867; cv=none; b=lupGp8X+/0VnQVKvdCzZrAVyEywvgixPya52VsnOq516ORpUWO/Q7XP2SIZDMMHBWs/FRR4WADIdG6OG+mdgVw4vZjcoI+7Imd5Bku8FGoVmN3xbS+3knHfuqDgD2ALHhBUSRw5j2ccVePGFPl0xAs0bI5wWg0+QFLl8Gusc4Zk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761117867; c=relaxed/simple; bh=aq4f1hDhOP4DGcybKEAs0T5HwBDkF1Yqlah0Y4hMm70=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=NpJpNpJEINONagNz+qKUkCYtdFlFvgqX+m3HJ704mDlOE/mMUa6CkIr6a4J6KGCvRInm9ejcpKqGq/wDOXhzreig9Afkw5kjejtoSmorWf0qyngyKTw0Jx0yqixheG8puoYYxNTaTso1oTNu5QLSGzgPgIFjhH8d4HlJs2tELww= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=WHnA9Oyz; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="WHnA9Oyz" Received: from [192.168.88.20] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 32218557; Wed, 22 Oct 2025 09:22:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1761117759; bh=aq4f1hDhOP4DGcybKEAs0T5HwBDkF1Yqlah0Y4hMm70=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=WHnA9OyzNbWDb9XQRanQ8mVUEQzUBQtj2B0bH7PLV5zghpTg4hsgQodYURlopAejr 4v+N2NU7SOSLGZ+1cQfZ6lQdD1bA5D64ttk0I2OJkKWn7a+TA7ayq4lvjb1kYrFj3W agQkV8xZDEuhSQylaVSeaZ1D5BMBmhraOHxUZUms= Message-ID: <6fac1b8a-1810-4fb8-8ea6-8628de57ce31@ideasonboard.com> Date: Wed, 22 Oct 2025 10:24:19 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] drm/bridge: samsung-dsim: Fix init order To: Inki Dae , Jagan Teki , Marek Szyprowski , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Aradhya Bhatia , Dmitry Baryshkov Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Hiago De Franco , Francesco Dolcini References: <20250619-samsung-dsim-fix-v1-1-6b5de68fb115@ideasonboard.com> Content-Language: en-US From: Tomi Valkeinen Autocrypt: addr=tomi.valkeinen@ideasonboard.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit Hi samsung-dsim maintainers, On 19/06/2025 15:27, Tomi Valkeinen wrote: > The commit c9b1150a68d9 ("drm/atomic-helper: Re-order bridge chain > pre-enable and post-disable") changed the order of enable/disable calls. > Previously the calls (on imx8mm) were: > > mxsfb_crtc_atomic_enable() > samsung_dsim_atomic_pre_enable() > samsung_dsim_atomic_enable() > > now the order is: > > samsung_dsim_atomic_pre_enable() > mxsfb_crtc_atomic_enable() > samsung_dsim_atomic_enable() > > On imx8mm (possibly on imx8mp, and other platforms too) this causes two > issues: > > 1. The DSI PLL setup depends on a refclk, but the DSI driver does not > set the rate, just uses it with the rate it has. On imx8mm this refclk > seems to be related to the LCD controller's video clock. So, when the > mxsfb driver sets its video clock, DSI's refclk rate changes. > > Earlier this mxsfb_crtc_atomic_enable() set the video clock, so the PLL > refclk rate was set (and didn't change) in the DSI enable calls. Now the > rate changes between DSI's pre_enable() and enable(), but the driver > configures the PLL in the pre_enable(). > > Thus you get a black screen on a modeset. Doing the modeset again works, > as the video clock rate stays the same. > > 2. The image on the screen is shifted/wrapped horizontally. I have not > found the exact reason for this, but the documentation seems to hint > that the LCD controller's pixel stream should be enabled first, before > setting up the DSI. This would match the change, as now the pixel stream > starts only after DSI driver's pre_enable(). > > The main function related to this issue is samsung_dsim_init() which > will do the clock and link configuration. samsung_dsim_init() is > currently called from pre_enable(), but it is also called from > samsung_dsim_host_transfer() to set up the link if the peripheral driver > wants to send a DSI command. > > This patch fixes both issues by moving the samsung_dsim_init() call from > pre_enable() to enable(). > > However, to deal with the case where the samsung_dsim_init() has already > been called from samsung_dsim_host_transfer() and the refclk rate has > changed, we need to make sure we re-initialize the DSI with the new rate > in enable(). This is achieved by clearing the DSIM_STATE_INITIALIZED > flag and uninitializing the clocks and irqs before calling > samsung_dsim_init(). > > Fixes: c9b1150a68d9 ("drm/atomic-helper: Re-order bridge chain pre-enable and post-disable") > Reported-by: Hiago De Franco > Signed-off-by: Tomi Valkeinen Can this be merged? Tomi > --- > drivers/gpu/drm/bridge/samsung-dsim.c | 29 +++++++++++++++++++---------- > 1 file changed, 19 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c > index f2f666b27d2d..cec383d8946d 100644 > --- a/drivers/gpu/drm/bridge/samsung-dsim.c > +++ b/drivers/gpu/drm/bridge/samsung-dsim.c > @@ -1473,22 +1473,31 @@ static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge, > } > > dsi->state |= DSIM_STATE_ENABLED; > - > - /* > - * For Exynos-DSIM the downstream bridge, or panel are expecting > - * the host initialization during DSI transfer. > - */ > - if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) { > - ret = samsung_dsim_init(dsi); > - if (ret) > - return; > - } > } > > static void samsung_dsim_atomic_enable(struct drm_bridge *bridge, > struct drm_atomic_state *state) > { > struct samsung_dsim *dsi = bridge_to_dsi(bridge); > + int ret; > + > + /* > + * The DSI bridge may have already been initialized in > + * samsung_dsim_host_transfer(). It is possible that the refclk rate has > + * changed after that due to the display controller configuration, and > + * thus we need to reinitialize the DSI bridge to ensure the correct > + * clock settings. > + */ > + > + if (dsi->state & DSIM_STATE_INITIALIZED) { > + dsi->state &= ~DSIM_STATE_INITIALIZED; > + samsung_dsim_disable_clock(dsi); > + samsung_dsim_disable_irq(dsi); > + } > + > + ret = samsung_dsim_init(dsi); > + if (ret) > + return; > > samsung_dsim_set_display_mode(dsi); > samsung_dsim_set_display_enable(dsi, true); > > --- > base-commit: 7872997c048e989c7689c2995d230fdca7798000 > change-id: 20250619-samsung-dsim-fix-58c8ec8193e9 > > Best regards,