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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4801e886829sm111346115e9.8.2026.01.17.13.45.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 17 Jan 2026 13:45:41 -0800 (PST) Message-ID: <6fd412e1-31d4-4f8b-9aa3-e2d7423fca66@linaro.org> Date: Sat, 17 Jan 2026 21:45:31 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 4/8] media: qcom: camss: Initialize lanes after lane configuration is available To: david@ixit.cz, Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org References: <20260117-qcom-cphy-v3-0-8ce76a06f7db@ixit.cz> <20260117-qcom-cphy-v3-4-8ce76a06f7db@ixit.cz> From: Bryan O'Donoghue Content-Language: en-US In-Reply-To: <20260117-qcom-cphy-v3-4-8ce76a06f7db@ixit.cz> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 17/01/2026 15:36, David Heidelberg via B4 Relay wrote: > From: Petr Hodina > > The lanes must not be initialized before the driver has access to > the lane configuration, as it depends on whether D-PHY or C-PHY mode > is in use. Move the lane initialization to a later stage where the > configuration structures are available. > > Signed-off-by: Petr Hodina > Signed-off-by: David Heidelberg > --- > .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 91 ++++++++++++++-------- > 1 file changed, 57 insertions(+), 34 deletions(-) > > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > index f3a8625511e1e..9e8470358515f 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > @@ -1048,6 +1048,62 @@ static int csiphy_lanes_enable(struct csiphy_device *csiphy, > u8 val; > int i; > > + switch (csiphy->camss->res->version) { > + case CAMSS_845: > + { /* V4L2_MBUS_CSI2_DPHY */ > + regs->lane_regs = &lane_regs_sdm845[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845); > + } > + break; > + case CAMSS_2290: > + case CAMSS_6150: > + { /* V4L2_MBUS_CSI2_DPHY */ > + regs->lane_regs = &lane_regs_qcm2290[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290); > + } > + break; > + case CAMSS_7280: > + case CAMSS_8250: > + { /* V4L2_MBUS_CSI2_DPHY */ > + regs->lane_regs = &lane_regs_sm8250[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250); > + } > + break; > + case CAMSS_8280XP: > + { /* V4L2_MBUS_CSI2_DPHY */ > + regs->lane_regs = &lane_regs_sc8280xp[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp); > + } > + break; > + case CAMSS_X1E80100: > + { /* V4L2_MBUS_CSI2_DPHY */ > + regs->lane_regs = &lane_regs_x1e80100[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100); > + } > + break; > + case CAMSS_8550: > + { /* V4L2_MBUS_CSI2_DPHY */ > + regs->lane_regs = &lane_regs_sm8550[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550); > + } > + break; > + case CAMSS_8650: > + { /* V4L2_MBUS_CSI2_DPHY */ > + regs->lane_regs = &lane_regs_sm8650[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650); > + } > + break; > + case CAMSS_8300: > + case CAMSS_8775P: > + { /* V4L2_MBUS_CSI2_DPHY */ > + regs->lane_regs = &lane_regs_sa8775p[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p); > + } > + break; > + default: > + break; > + } > + > settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); > > val = 0; > @@ -1119,49 +1175,16 @@ static int csiphy_init(struct csiphy_device *csiphy) > return -ENOMEM; > > csiphy->regs = regs; > - regs->offset = 0x800; > regs->common_status_offset = 0xb0; > > switch (csiphy->camss->res->version) { > - case CAMSS_845: > - regs->lane_regs = &lane_regs_sdm845[0]; > - regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845); > - break; > - case CAMSS_2290: > - case CAMSS_6150: > - regs->lane_regs = &lane_regs_qcm2290[0]; > - regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290); > - break; > - case CAMSS_7280: > - case CAMSS_8250: > - regs->lane_regs = &lane_regs_sm8250[0]; > - regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250); > - break; > - case CAMSS_8280XP: > - regs->lane_regs = &lane_regs_sc8280xp[0]; > - regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp); > - break; > case CAMSS_X1E80100: > - regs->lane_regs = &lane_regs_x1e80100[0]; > - regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100); > - regs->offset = 0x1000; > - break; > case CAMSS_8550: > - regs->lane_regs = &lane_regs_sm8550[0]; > - regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550); > - regs->offset = 0x1000; > - break; > case CAMSS_8650: > - regs->lane_regs = &lane_regs_sm8650[0]; > - regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650); > regs->offset = 0x1000; > break; > - case CAMSS_8300: > - case CAMSS_8775P: > - regs->lane_regs = &lane_regs_sa8775p[0]; > - regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p); > - break; > default: > + regs->offset = 0x800; > break; > } > > Subject to testing. Reviewed-by: Bryan O'Donoghue --- bod