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Fri, 22 May 2026 02:22:51 -0700 (PDT) X-Received: by 2002:a17:903:1a07:b0:2bd:8822:d8cb with SMTP id d9443c01a7336-2beb063193emr31328745ad.23.1779441770665; Fri, 22 May 2026 02:22:50 -0700 (PDT) Received: from [10.217.198.242] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2beb56ca7fcsm11220795ad.27.2026.05.22.02.22.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 22 May 2026 02:22:50 -0700 (PDT) Message-ID: <6fd91379-4347-44b6-8514-3c1e66e12aca@oss.qualcomm.com> Date: Fri, 22 May 2026 14:52:45 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: "Maulik Shah (mkshah)" Subject: Re: [PATCH 3/5] irqchip/qcom-pdc: Configure PDC to pass through mode To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Linus Walleij , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Sneh Mankad References: <20260312-hamoa_pdc-v1-0-760c8593ce50@oss.qualcomm.com> <20260312-hamoa_pdc-v1-3-760c8593ce50@oss.qualcomm.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=DKm/JSNb c=1 sm=1 tr=0 ts=6a10206b cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=1v8zxqPQ2sg2QXuulHIA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: NJgiYZlwW66NkDpo3rU8Y0Nlkn3C6X9F X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIyMDA5MyBTYWx0ZWRfX1WabXASQ64ph VoUXzDQ301jlHybUT6P9fQIJZnU5oEpBWNo6XBUN4TqTA8ewCcyAWRp2PMvGyFZHVL+ktoij1Zt Bw9QNmD5NVSEJeo6Kig5gJnVlqgdTA4/xaHujlFIX3+Pvli1J5wmN4/UgVxrwZH5exjsjb8tfAe VWn4V1tQuD4US1+6xfJZMykLE3mcEnB5JFDgKmQrtGIhG7Noy0h5o8akzfJbPucHt7Dfbc0LWei ODqyoAZKZJ43S1ddEJFT3Nvd44E2BgQPmoo7GkP3g7DVUbUUGdqIbXoN6kkF5D5QY7ZJUT1ytSo IGxboC99rOHtQNRAU5dCJ2pNTKZOqxWwnrG9XWhTc/Uj3HMAL87p+WPbF0xIpXLyaC14XtVjdxo py0bju2gXIeVeMXx57K/Pr8Ra44gSfGsrZUtapHnDz7ryPF2DSukc5Dq0vGpZgyNqIWhok2tiAg xHsCu7J8Z8vzQSQoEvA== X-Proofpoint-ORIG-GUID: NJgiYZlwW66NkDpo3rU8Y0Nlkn3C6X9F X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-22_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 spamscore=0 phishscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605220093 On 3/24/2026 8:22 AM, Bjorn Andersson wrote: > On Thu, Mar 12, 2026 at 09:26:37PM +0530, Maulik Shah wrote: >> There are two modes PDC irqchip supports pass through mode and secondary >> controller mode. >> >> All PDC irqchip supports pass through mode in which both Direct SPIs and >> GPIO IRQs (as SPIs) are sent to GIC without latching at PDC. >> >> Newer PDCs (v3.0 onwards) also support additional secondary controller mode >> where PDC latches GPIO IRQs and sends to GIC as level type IRQ. Direct SPIs >> still works same as pass through mode without latching at PDC even in >> secondary controller mode. >> >> All the SoCs so far default uses pass through mode with the exception of >> x1e. x1e PDC may be set to secondary controller mode for builds on CRD >> boards whereas it may be set to pass through mode for IoT-EVK. >> >> There is no way to read which current mode it is set to and make PDC work >> in respective mode as the read access is not opened up for non secure >> world. There is though write access opened up via SCM write API to set the >> mode. >> >> Configure PDC mode to pass through mode for all x1e based boards via SCM >> write. >> > > You're failing to mention that the SCM interface was not present in > initially shipping Windows firmware, which would result in you breaking > those devices. I will mention same in the v2 series commit message. This series has also been tested on older firmware and the scm_write failure path is handled properly, so existing devices will not be braked. > > If you're certain that this change is available to all users, you can > argue that this is acceptable - but omitting this from the commit > message isn't. Not certain. In v2 series adding the secondary mode support which allows to hit deepest low power mode irrespective of the old/new firmware. Thanks, Maulik