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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a0a3e80sm2226480566b.47.2025.08.12.07.26.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Aug 2025 07:26:04 -0700 (PDT) Message-ID: <6ffa8d6f-d5fb-4a94-ab7c-1a923cae1332@oss.qualcomm.com> Date: Tue, 12 Aug 2025 16:26:02 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v2 1/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5 To: Krzysztof Kozlowski , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , Vikash Garodia Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250806-b4-sm8750-iris-dts-v2-0-2ce197525eed@linaro.org> <20250806-b4-sm8750-iris-dts-v2-1-2ce197525eed@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: j030vVbYY6x3VLnmpwjFJplvapsOaKjB X-Proofpoint-ORIG-GUID: j030vVbYY6x3VLnmpwjFJplvapsOaKjB X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDA2OCBTYWx0ZWRfX54Wjcy87ngPI WKJU/xOdtZRuMmLOt87z7pSrE7Qhc5hfja7CaFkt78sS/bFbu/XDdSUM+NsXBqbKC/vgJkfGoe5 lRPtDBSBhYmyEJMRyug9hj9kXFuxXi0TeAkJVawff+viz8kXIJIB6kk8aSRzpeoLE8kOW9M+0EJ 4FKeLb3h/7uvEZSus8Op8/VkTgpQtS33xP0MaVV9mpBph8FzcrrY4K/l/SOs8qpQRKpPdfMwkVb IX4sZ9FgJz6dUor825T49eJe1tCtbmOxxV7WCjbRxiAtq3JR9KLN1jOXCErzaxJv7MdVkJIbRaa edMpOg92JcE8t/F1wl1sdTmu9yNqap8H3HFSeV0mFjjIpNDywXlav3uV5pp9SaRZZ8EKK049aE5 9nEXhiDt X-Authority-Analysis: v=2.4 cv=YMafyQGx c=1 sm=1 tr=0 ts=689b4efe cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=KKAkSRfTAAAA:8 a=9XIazU3Zd_7FZfIRWW0A:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_07,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 priorityscore=1501 spamscore=0 suspectscore=0 adultscore=0 impostorscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110068 On 8/12/25 4:24 PM, Krzysztof Kozlowski wrote: > On 12/08/2025 16:21, Konrad Dybcio wrote: >> On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote: >>> Add Iris video codec to SM8750 SoC, which comes with significantly >>> different powering up sequence than previous SM8650, thus different >>> clocks and resets. For consistency keep existing clock and clock-names >>> naming, so the list shares common part. >>> >>> Signed-off-by: Krzysztof Kozlowski >>> >>> --- >> >> [...] >> >>> + iris_opp_table: opp-table { >>> + compatible = "operating-points-v2"; >>> + >>> + opp-240000000 { >>> + opp-hz = /bits/ 64 <240000000>; >>> + required-opps = <&rpmhpd_opp_low_svs_d1>, >>> + <&rpmhpd_opp_low_svs_d1>; >>> + }; >>> + >>> + opp-338000000 { >>> + opp-hz = /bits/ 64 <338000000>; >>> + required-opps = <&rpmhpd_opp_low_svs>, >>> + <&rpmhpd_opp_low_svs>; >>> + }; >>> + >>> + opp-420000000 { >>> + opp-hz = /bits/ 64 <420000000>; >>> + required-opps = <&rpmhpd_opp_svs>, >>> + <&rpmhpd_opp_svs>; >>> + }; >>> + >>> + opp-444000000 { >>> + opp-hz = /bits/ 64 <444000000>; >>> + required-opps = <&rpmhpd_opp_svs_l1>, >>> + <&rpmhpd_opp_svs_l1>; >>> + }; >>> + >>> + opp-533333334 { >>> + opp-hz = /bits/ 64 <533333334>; >>> + required-opps = <&rpmhpd_opp_nom>, >>> + <&rpmhpd_opp_nom>; >>> + }; >> >> There's an additional OPP: 570 MHz @ NOM_L1 >> >> +Dmitry, Vikash, please make sure you're OK with the iommu entries > > > That opp has troubles with clock, so would need some fixed in videocc or > iris, AFAIK. Otherwise you will just PM OPP failures. I can add it > though, at the end DTS should be independent of drivers. :) Weird, there's an entry in the frequency table for it (well, * 3 the rate) and it comes out of the same PLL as other ones.. what sort of opp failures do you see? Konrad