From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-170.mta0.migadu.com (out-170.mta0.migadu.com [91.218.175.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F21BF27F18F; Thu, 8 Jan 2026 23:00:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.170 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767913236; cv=none; b=VZBlXOzBVQiDYc/riwozUFTIRNgI8bo7hZwDxe6M8kS1HaRl8FvdlhtTLbx8kX68lJJNQbfmn8wKBgvyXrV4DUoJcayEyIvVoPQmot74WQ2fiNYUTY2ceO9dm5r5J2lnTpRBkQfCeLya9/Qz2kB3+lNSoaMGCgEU95/wr8A6Y7g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767913236; c=relaxed/simple; bh=Gmp7oxzoMMQ+4FOB0OmFFTH7yDV+Rd4MYUw4zlyLzq4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=cIT9Fl5u2TcRbVCrmQrRMptkY/3kjCDFOUuChWTfA8jvBmXKyzr88Ph7NFZ2vtySN7hIOQflExxFo0KGVkpQCLsJCHpyEKJoYzkGxMZMPfz6SuHyn/9pf6ZxzMOdycv1/IAk4s6VeYlan4iy4mfCwtfN+VQZ+ficza4GCJKjdY0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=W7HLm4CL; arc=none smtp.client-ip=91.218.175.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="W7HLm4CL" Message-ID: <702e4696-5ff6-4c72-bce4-1a9a8ee1ba18@packett.cool> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1767913222; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3Y93ff+hEOI+QHoGj9/iWZX4epwSGuXWyQ3WAZwL30k=; b=W7HLm4CLof9hJBlf9kF+Ck/RzjHe1jNiMASMK39UJHeXZndB5FTA5SHTAXtUKm8ZZwjZcY NkoZcf1HOarv5Nn2EWog/W2fzVzLbDrrhezpiO7+2SIPgLhhSKiPJqZ0YMnY1XEVX9gjCF zscvZj3lfYU7Kj7ir0WhOivJQ/c5VhIuFMRLLKcmf3xF0UoTwQi+aNaA2sbv5ejKyB75MB wXZ2rgUijijpYmbPGs4cHFhPWw0Hz/LuE5WiOnSCnbLfj1mN4e4d9zAnKKFTao24uO5ySB uYtY841b4cR62R4Zf5xNP6YeyPdAcDbxdm2Ag8nTHcpt480Vo24YxnLs0vLGgA== Date: Thu, 8 Jan 2026 20:00:13 -0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH v2] clk: qcom: dispcc-sdm845: Enable parents for pixel clocks To: petr.hodina@protonmail.com, Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Michael Turquette , Stephen Boyd , David Heidelberg , Taniya Das Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, phone-devel@vger.kernel.org References: <20260107-stability-discussion-v2-1-ef7717b435ff@protonmail.com> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Val Packett In-Reply-To: <20260107-stability-discussion-v2-1-ef7717b435ff@protonmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Migadu-Flow: FLOW_OUT On 1/7/26 8:44 AM, Petr Hodina via B4 Relay wrote: > From: Petr Hodina > > Add CLK_OPS_PARENT_ENABLE to MDSS pixel clock sources to ensure parent > clocks are enabled during clock operations, preventing potential > stability issues during display configuration. > > Fixes: 81351776c9fb ("clk: qcom: Add display clock controller driver for SDM845") > Signed-off-by: Petr Hodina > --- > We are currently running the latest linux-next snapshots (next-202511* > and next-202512*) and have encountered random freezes and crashes on the > Pixel 3, as well as crash dumps on the OnePlus 6 and 6T. > > This commit fixes the stability issue. I've checked other SDM dispcc > files and they also contain this configuration. Hm, we don't have this flag set in dispcc-x1e80100.c either! The only random freeze we have on that platform seems related to PCIe ASPM with NVMe drives, but during display configuration.. *extremely* rarely, but the eDP display output can get stuck on a blue screen. Many run with clk_ignore_unused for the early uefi framebuffer though. ~val