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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b876fe420ffsm101881666b.21.2026.01.14.05.45.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Jan 2026 05:45:18 -0800 (PST) Message-ID: <702ea825-dda1-495a-a72e-05b45491892a@oss.qualcomm.com> Date: Wed, 14 Jan 2026 14:45:14 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/4] arm64: dts: qcom: Introduce Glymur base dtsi To: Pankaj Patil , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jyothi Kumar Seerapu , Maulik Shah , Sibi Sankar , Taniya Das , Kamal Wadhwa , Qiang Yu , Manaf Meethalavalappu Pallikunhi , Jishnu Prakash , Abel Vesa References: <20260112-upstream_v3_glymur_introduction-v4-0-8a0366210e02@oss.qualcomm.com> <20260112-upstream_v3_glymur_introduction-v4-3-8a0366210e02@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260112-upstream_v3_glymur_introduction-v4-3-8a0366210e02@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=BOW+bVQG c=1 sm=1 tr=0 ts=69679df1 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=-jCX82INsGBcRmD4oUQA:9 a=uVu2OgOm8jta4EFE:21 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-ORIG-GUID: wSY23lEYSM5eHX2Crv7_iOj0hYOCTEHC X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTE0MDExNSBTYWx0ZWRfX+HAj4B8fq8IH +R1fZKDNC3E8CidurtYRkIIYuaDice7ckERH8VKpbaHL0OaCNSPN/fTQFS7vkH/7mtO7qPbaFsZ t55wZei/R6pgRMPDSpGdHyICEyNq1HkH6zdYZDHOS0NApjPnvL5Tbg88yLft1lT8gBntyMPDnWE 6c2oTqLVqlo3naDA5VjMns+L6UtO8wX3xtaEGq9eHuZX3273ZDU76ND9moXEZI41788Y5dRfnve 40jfderFM/PDYt+zekpOlrzaErQJUPG0cAs8fSi8sgLzQx8XD+l5NVnhI0FtjphF/YGJjE+pFTO +8IHYvql/yKZ1Kq/n38uS1tCdkOnyh6mEeVy4KEYk8hFyciQ1S2tuJU4aGf9yndZ5KlbExdy3L1 wcxYJaXhanR0fTEJ2q/fkEgTqbETX8xZ/KytoflT8l1Bv8i3tjHQZyc89kRBvWiRoswrePsdvtm ODXsFksA0THnHMu8Kvw== X-Proofpoint-GUID: wSY23lEYSM5eHX2Crv7_iOj0hYOCTEHC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-14_04,2026-01-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601140115 On 1/12/26 1:22 PM, Pankaj Patil wrote: > Introduce the base device tree support for Glymur – Qualcomm's > next-generation compute SoC. The new glymur.dtsi describes the core SoC > components, including: > > - CPUs and CPU topology > - Interrupt controller and TLMM > - GCC,DISPCC and RPMHCC clock controllers > - Reserved memory and interconnects > - APPS and PCIe SMMU and firmware SCM > - Watchdog, RPMHPD, APPS RSC and SRAM > - PSCI and PMU nodes > - QUPv3 serial engines > - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS > - PDP0 mailbox, IPCC and AOSS > - Display clock controller > - SPMI PMIC arbiter with SPMI0/1/2 buses > - SMP2P nodes > - TSENS and thermal zones (8 instances, 92 sensors) [...] > + uart22: serial@898000 { > + compatible = "qcom,geni-uart"; > + reg = <0x0 0x00898000 0x0 0x4000>; > + interrupts = ; > + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; > + clock-names = "se"; > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config"; stray \t [...] > + i2c8: i2c@a80000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x00a80000 0x0 0x4000>; > + interrupts = ; > + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; > + clock-names = "se"; > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, > + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, > + <&gpi_dma1 1 0 QCOM_GPI_I2C>; > + dma-names = "tx", > + "rx"; > + pinctrl-0 = <&qup_i2c8_data_clk>; > + pinctrl-names = "default"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; nit: generally we try to put an \n before status [...] > + pcie4_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + /* GEN 1 x1 */ > + opp-2500000 { > + opp-hz = /bits/ 64 <2500000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + opp-peak-kBps = <250000 1>; > + }; > + > + /* GEN 1 x2 and GEN 2 x1 */ > + opp-5000000 { > + opp-hz = /bits/ 64 <5000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + opp-peak-kBps = <500000 1>; > + }; I see that this DT doesn't define opp-level for PCIe OPP entries - could you please quickly check with some PCIe folks whether that's intentional (there are cases where it's not necessary because the controller doesn't need a different vote to operate an effectively-same-bw OPP with different link width and gen) [...] > + system-cache-controller@20400000 { > + compatible = "qcom,glymur-llcc"; > + reg = <0x0 0x21800000 0x0 0x100000>, > + <0x0 0x21a00000 0x0 0x100000>, > + <0x0 0x21c00000 0x0 0x100000>, > + <0x0 0x21e00000 0x0 0x100000>, > + <0x0 0x22800000 0x0 0x100000>, > + <0x0 0x22a00000 0x0 0x100000>, > + <0x0 0x22c00000 0x0 0x100000>, > + <0x0 0x22e00000 0x0 0x100000>, > + <0x0 0x23800000 0x0 0x100000>, > + <0x0 0x23a00000 0x0 0x100000>, > + <0x0 0x23c00000 0x0 0x100000>, > + <0x0 0x23e00000 0x0 0x100000>, > + <0x0 0x20400000 0x0 0x100000>, > + <0x0 0x20600000 0x0 0x100000>; > + > + reg-names = "llcc0_base", stray \n Konrad