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Thu, 23 Oct 2025 01:42:24 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG2rBCLzjTPJc/nY65doA/UHQAoORgCvBAhguw9qkE0tE9g8A0pq4eU8cfSTj3QkVtEG+RGhA== X-Received: by 2002:a05:6a21:3988:b0:2b7:e136:1f30 with SMTP id adf61e73a8af0-33c626aecb4mr2160417637.55.1761208944214; Thu, 23 Oct 2025 01:42:24 -0700 (PDT) Received: from [10.217.217.147] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-33e2247a7f1sm5037500a91.14.2025.10.23.01.42.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 Oct 2025 01:42:23 -0700 (PDT) Message-ID: <703cfc97-ff4b-47f5-9f14-fb3ea4f68f7a@oss.qualcomm.com> Date: Thu, 23 Oct 2025 14:12:18 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/9] Add support for Clock controllers for Kaanapali To: Bjorn Andersson , Jingyi Wang Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com References: <20250924-knp-clk-v1-0-29b02b818782@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDIxMDE2NyBTYWx0ZWRfX2ufzCrOG3h7U alV0YZ5sQR5efIFu5G0lmZmXPqYj8+CEGdNr/9wIOL3+tTVhCukd8WbTavyGpS4brZh1y9eFk1U 1nqyOPwS/c9/51KhUD/tP6dpTytUwiVfW/m3HrNOMX4wCXlQgWO+v1Oa/+Dy2eLb6b/0+qERW0C xNaNHGtfCMO85cYdkNLkiWua+OZP1gY3RYZR4GX7kOD4PKoEU8tcAiSxK5LjDDGht3AjeI8wRA1 BSAY02u6RwnlUIqzqM8iBgtcgTphGSQ8NgV3Fx+I6OeS2AW2MKPkmEkT1Y53rxE1RUG/T3MD4Wy u0N5N+6vUjZzBGcUS+ZJ6PHyOx8tP6ynEolT2EjnNL8PocEhPGznOcLy2RjbtAFI+88zVGQFY/Z 0PiTqZEMe5/Ra4qrM8PnS3ZsUgUZuQ== X-Proofpoint-ORIG-GUID: 3_gTHK5SuV3eDU4i32xmm6cc3A3_ffV3 X-Authority-Analysis: v=2.4 cv=WYUBqkhX c=1 sm=1 tr=0 ts=68f9ea72 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=M_Sh8l_qeD7bdTgo-sgA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-GUID: 3_gTHK5SuV3eDU4i32xmm6cc3A3_ffV3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-22_08,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 bulkscore=0 impostorscore=0 spamscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510210167 On 10/23/2025 3:23 AM, Bjorn Andersson wrote: > On Wed, Sep 24, 2025 at 03:58:52PM -0700, Jingyi Wang wrote: >> Add support for Global clock controller(GCC), TCSR and the RPMH clock >> controller for the Qualcomm Kaanapali SoC. And update the PLL support. >> >> Signed-off-by: Jingyi Wang >> --- >> Taniya Das (9): >> dt-bindings: clock: qcom-rpmhcc: Add RPMHCC for Kaanapali >> dt-bindings: clock: qcom: Document the Kaanapali TCSR Clock Controller >> dt-bindings: clock: qcom: Add Kaanapali Global clock controller >> clk: qcom: rpmh: Add support for Kaanapali rpmh clocks >> clk: qcom: Update TCSR clock driver for Kaanapali >> clk: qcom: Add support for Global clock controller on Kaanapali >> clk: qcom: clk-alpha-pll: Update the PLL support for cal_l >> clk: qcom: clk-alpha-pll: Add support for controlling Pongo EKO_T PLL >> clk: qcom: clk-alpha-pll: Add support for controlling Rivian PLL > > The series adds rpmh, tcsr and global clock controllers, and then it > adds support for cal_l and two new PLL types. > This ordering I will fix in the next patch. > I assumed that meant that the order of the patches was wrong, but I > can't find anything in this series that depend on these 3 last patches. > These were originally part of the Multimedia clock series and got introduced after Jingyi mentioned they need to be moved to this series. I can update the order of the patches to RPMHCC, TCSRCC, PLL code changes and then the GCC clock controller if that seems okay for these patches, please suggest. > They seems to just add dead code? > > Regards, > Bjorn > >> >> .../devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + >> .../bindings/clock/qcom,sm8550-tcsr.yaml | 1 + >> .../devicetree/bindings/clock/qcom,sm8750-gcc.yaml | 8 +- >> drivers/clk/qcom/Kconfig | 9 + >> drivers/clk/qcom/Makefile | 1 + >> drivers/clk/qcom/clk-alpha-pll.c | 20 +- >> drivers/clk/qcom/clk-alpha-pll.h | 7 + >> drivers/clk/qcom/clk-rpmh.c | 39 + >> drivers/clk/qcom/gcc-kaanapali.c | 3541 ++++++++++++++++++++ >> drivers/clk/qcom/tcsrcc-sm8750.c | 34 +- >> include/dt-bindings/clock/qcom,kaanapali-gcc.h | 241 ++ >> 11 files changed, 3897 insertions(+), 5 deletions(-) >> --- >> base-commit: ae2d20002576d2893ecaff25db3d7ef9190ac0b6 >> change-id: 20250917-knp-clk-c60d94492863 >> >> Best regards, >> -- >> Jingyi Wang >> -- Thanks, Taniya Das