Re: [PATCH] PCI: stm32: Fix LTSSM EP race with start link.

[Christian Bruel <christian.bruel@foss.st.com>]

On 11/18/25 22:28, Bjorn Helgaas wrote:
> [+cc Lukas in case I got the pciehp part wrong]
> 

> 
> To back up here, I'm trying to understand the race.
> 
> IIUC the relevant events are link training and register init.  In the
> current stm32 EP driver, link training can start when the EP userspace
> writes to the 'start' configfs file.  And the register init happens
> when stm32_pcie_ep_perst_irq_thread() calls
> dw_pcie_ep_init_registers().
> 
> So I guess the problem is when the EP userspace enables the LTSSM
> before the host deasserts PERST#?  And the link train may complete
> before stm32_pcie_ep_perst_irq_thread() runs?

The sequence also violated the spec (4.0, Section 6.6.1 "Conventional 
Reset"), because it allowed the endpoint to enter the Detect state 
before PERST# is deasserted

> 
> And the fix here is to delay enabling the EP LTSSM until after
> stm32_pcie_perst_deassert() calls dw_pcie_ep_init_registers()?
> 

> 
> I think we would prefer if the host would enumerate the endpoint
> whenever the endpoint becomes ready, even if that is after the host's
> initial enumeration, but I guess that's only possible if the host is
> notified when the link comes up.
> 
> The main mechanism for that is hotplug, i.e., pciehp handles presence
> detect and link layer state changed events, both of which are managed
> by the PCIe Slot register set.  Those registers are optional and may
> not be implemented, e.g., if a Root Port is connected to a
> system-integrated device.
> 
> But if they *are* implemented, I hope that pciehp makes it so no user
> intervention on the host side is required.
>


I suppose that hotplug cannot be implemented without some kind of 
presence detection signal from the EP (PRSNT#, ...) ? For now we have no 
  implementation to support this (from gpio or other).

However, using a PC host, I observe that when I resume the host from 
PCIe autosuspend, for example, with 'lspci', PERST# is deasserted, and 
the stm32 PCIe EP device is correctly enumerated without a manual 
rescan. So thanks to power management, a device can be enumerated 
asynchronously but when requested, not when ready.