From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 062B43955C0 for ; Tue, 2 Jun 2026 21:02:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780434147; cv=none; b=WGmjP7rF0hqJ8Bd+ldtVzwL4zNBll1AEpsTThtvSme4oG70Ma0+Ff+d8iZpqa7quQifoUdZxNX0XsbldKnDBQL7eiCJKPBsmfOpLd2PL+II/RSoLiEJsupKK+5eeSsVH5Yn/Fx65iURxap9knCRNrrqk7IqLEKJomPNehHZHQmw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780434147; c=relaxed/simple; bh=YmdFxDiQRLYjUBKccLdhO4F6nshK7wzXjX/mx1d/POw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HBpx8NoQ+PJkP8oXYIJiDSqS6olgrVVhK8J8WPOf6a8jgQDMUeuk22y5C5yBpfywhogBndI2M8pbYZMGBMi3zUh6a9A2A3iPyLEoJsvXmYaCh+737IYMbB/G8kwxnlv7994cI7ylGC7k4UAJn7uC0TmhIu4IkFtJakeYsPRxZno= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=BHMrXHkr; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="BHMrXHkr" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Type:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To; bh=NyPSyRLUOFZ5pN/SoGqXQdqwGa+JGoFeCCOZJivTsn8=; b=BHMrXHkrVaEX4fAoOWSvgiF4om /u4wFEh0HbB21HLqcwBI2wNR0UQaqIVhsmYq6hGG4F9YMwwFAf14hXCsvvuq1TYGAhT3Omb0jrKKz XVCfVXbdPhkqFA6jBE8SF6t96CjwxGI6As7ZDHpha6GBKKGcYH8yTssbdFxYbLtt1fFsyrbe/n89Y 2tJqoqQ0inusrDVXbJ5NrenuDVc6pAJUr8aN1jqyvX1caeVuAgXvUlR6pA+pkZ2UZpq41NqljO4e8 WhPKFNdOMUNMyIsfKAB34adwmhRYiYfjaYwgr54UuajxtVRcsfFT6CDV/RAXmp/zL7gKKi+gXYXXS ZUkudMFg==; From: Heiko Stuebner To: Sandy Huang , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Guochun Huang , Chaoyi Chen Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Chaoyi Chen Subject: Re: [PATCH 2/2] drm/rockchip: dsi: Add dphy_get_timing support for multiple PHY types Date: Tue, 02 Jun 2026 23:02:13 +0200 Message-ID: <7091445.e8TTKsaY2g@phil> In-Reply-To: <20260324085838.90-2-kernel@airkyi.com> References: <20260324085838.90-1-kernel@airkyi.com> <20260324085838.90-2-kernel@airkyi.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Am Dienstag, 24. M=C3=A4rz 2026, 09:58:38 Mitteleurop=C3=A4ische Sommerzeit= schrieb Chaoyi Chen: > From: Chaoyi Chen >=20 > Currently, there are generally two types of DPHY for Rockchip. One is > the DPHY used by RK3288/RK3399, whose timing is described by Table A-3 > High-Speed Transition Times in the databook. The other is the DPHY used > by PX30 and its successors. If its timing is still described using > RK3288/RK3399, it may not perform correctly on some DSI panel. >=20 > Add dphy_get_timing for different D-PHY types to adapt to timing > differences. >=20 > Signed-off-by: Chaoyi Chen > --- > .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 45 ++++++++++++++++++- > 1 file changed, 43 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gp= u/drm/rockchip/dw-mipi-dsi-rockchip.c > index d3bacfae174e..2d1c9e54ff85 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c > @@ -247,6 +247,7 @@ enum { > BIASEXTR_127_7, > }; > =20 > +struct dw_mipi_dsi_rockchip; > struct rockchip_dw_dsi_chip_data { > u32 reg; > =20 > @@ -262,6 +263,9 @@ struct rockchip_dw_dsi_chip_data { > u32 lanecfg2_grf_reg; > u32 lanecfg2; > =20 > + int (*dphy_get_timing)(struct dw_mipi_dsi_rockchip *dsi, unsigned int l= ane_mbps, > + struct dw_mipi_dsi_dphy_timing *timing); > + > int (*dphy_rx_init)(struct phy *phy); > int (*dphy_rx_power_on)(struct phy *phy); > int (*dphy_rx_power_off)(struct phy *phy); > @@ -721,8 +725,9 @@ static struct hstt hstt_table[] =3D { > }; > =20 > static int > -dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, > - struct dw_mipi_dsi_dphy_timing *timing) > +dw_mipi_dsi_phy_rk3288_get_timing(struct dw_mipi_dsi_rockchip *dsi, > + unsigned int lane_mbps, > + struct dw_mipi_dsi_dphy_timing *timing) > { > int i; > =20 > @@ -738,6 +743,32 @@ dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned= int lane_mbps, > return 0; > } > =20 > +static const struct dw_mipi_dsi_dphy_timing dphy_timing_px30 =3D { > + .clk_lp2hs =3D 0x40, > + .clk_hs2lp =3D 0x40, > + .data_lp2hs =3D 0x10, > + .data_hs2lp =3D 0x14, > +}; so just to make sure, the timing on the px30 (and later) variant is the same for all lane speeds? Please include that bit in the commit description Thanks Heiko