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Mon, 12 Jan 2026 07:06:53 -0800 (PST) Message-ID: <7097507636282e4613d324ff5acb74eb747d519b.camel@linaro.org> Subject: Re: [PATCH v2 4/5] clk: samsung: gs101: add support for Display Process Unit (DPU) clocks From: =?ISO-8859-1?Q?Andr=E9?= Draszik To: Peter Griffin , Tudor Ambarus , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , kernel-team@android.com, Will McVicker , Juan Yescas , Doug Anderson Date: Mon, 12 Jan 2026 15:07:20 +0000 In-Reply-To: <20260112-dpu-clocks-v2-4-bd00903fdeb9@linaro.org> References: <20260112-dpu-clocks-v2-0-bd00903fdeb9@linaro.org> <20260112-dpu-clocks-v2-4-bd00903fdeb9@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-2+build3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Mon, 2026-01-12 at 14:16 +0000, Peter Griffin wrote: > cmu_dpu is the clock management unit used for the Display Process Unit > block. It generates clocks for image scaler, compressor etc. >=20 > Add support for the muxes, dividers and gates in cmu_dpu. >=20 > Signed-off-by: Peter Griffin > --- > Changes in v2: > =C2=A0- Update gout_dpu_dpu_pclk to gout_dpu_gpc_dpu_pclk (Peter) > =C2=A0- Fix dout_dpu_busp parent (Peter) > --- > =C2=A0drivers/clk/samsung/clk-gs101.c | 283 +++++++++++++++++++++++++++++= +++++++++++ > =C2=A01 file changed, 283 insertions(+) >=20 > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs= 101.c > index 8551289b46eb88ec61dd1914d0fe782ae6794000..b38c6c8749aae42319d2004ff= 5ffbc9a19320cac 100644 > --- a/drivers/clk/samsung/clk-gs101.c > +++ b/drivers/clk/samsung/clk-gs101.c > @@ -25,6 +25,7 @@ > =C2=A0#define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1) > =C2=A0#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1) > =C2=A0#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1) > +#define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_DPU_PCLK + 1) Between APM and HSI0 to keep alphabetic ordering :-) > =C2=A0 > =C2=A0#define GS101_GATE_DBG_OFFSET 0x4000 > =C2=A0#define GS101_DRCG_EN_OFFSET=C2=A0 0x104 > @@ -4426,6 +4427,285 @@ static const struct samsung_cmu_info peric1_cmu_i= nfo __initconst =3D { > =C2=A0 .drcg_offset =3D GS101_DRCG_EN_OFFSET, > =C2=A0}; > =C2=A0 > +/* ---- CMU_DPU --------------------------------------------------------= ----- */ I'll do a full review later, but this new block should also be between existing CMU_APM and CMU_HSI0 blocks to keep alphabetic ordering. Cheers, Andre'