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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SA2PEPF00003AE8.mail.protection.outlook.com (10.167.248.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.9 via Frontend Transport; Mon, 17 Nov 2025 19:00:47 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Mon, 17 Nov 2025 11:00:45 -0800 Received: from [172.31.184.125] (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Mon, 17 Nov 2025 11:00:42 -0800 Message-ID: <7099a373-8d6c-4c67-806c-84b50315f160@amd.com> Date: Tue, 18 Nov 2025 00:30:36 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [tip: sched/core] sched/fair: Skip sched_balance_running cmpxchg when balance is not due To: Tim Chen , Shrikanth Hegde , , "Peter Zijlstra (Intel)" CC: , Chen Yu , Vincent Guittot , Srikar Dronamraju , Mohini Narkhede , References: <6fed119b723c71552943bfe5798c93851b30a361.1762800251.git.tim.c.chen@linux.intel.com> <176312274812.498.6548506845675120622.tip-bot2@tip-bot2> Content-Language: en-US From: K Prateek Nayak In-Reply-To: Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2025 19:00:47.0211 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e2089910-025f-4e25-1dd5-08de260b9e05 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7255 On 11/18/2025 12:25 AM, Tim Chen wrote: >> I wondered what is really different since the tim's v4 boots fine. >> There is try instead in the tip, i think that is messing it since likely >> we are dereferencing 0? >> >> >> With this diff it boots fine. >> >> --- >> diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c >> index aaa47ece6a8e..01814b10b833 100644 >> --- a/kernel/sched/fair.c >> +++ b/kernel/sched/fair.c >> @@ -11841,7 +11841,7 @@ static int sched_balance_rq(int this_cpu, struct rq *this_rq, >> } >> >> if (!need_unlock && (sd->flags & SD_SERIALIZE)) { >> - if (!atomic_try_cmpxchg_acquire(&sched_balance_running, 0, 1)) > > The second argument of atomic_try_cmpxchg_acquire is "int *old" while that of atomic_cmpxchg_acquire > is "int old". So the above check would result in NULL pointer access. Probably have > to do something like the following to use atomic_try_cmpxchg_acquire() > > int zero = 0; > if (!atomic_try_cmpxchg_acquire(&sched_balance_running, &zero, 1)) Peter seems to have refreshed tip:sched/core with above but is there any advantage of using atomic_try_cmpxchg_acquire() as opposed to plain old atomic_cmpxchg_acquire() and then checking the old value it returns? That zero variable serves no other purpose and is a bit of an eyesore IMO. > > Otherwise we should do atomic_cmpxchg_acquire() as below > >> + if (!atomic_cmpxchg_acquire(&sched_balance_running, 0, 1)) > -- Thanks and Regards, Prateek