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Wed, 02 Jul 2025 08:55:44 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5628thfG015431 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 2 Jul 2025 08:55:43 GMT Received: from [10.217.217.75] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 2 Jul 2025 01:55:40 -0700 Subject: Re: [PATCH V2 1/2] arm64: dts: qcom: Add eMMC support for qcs8300 To: Konrad Dybcio , , , , , CC: , , References: <20250619070224.23428-1-quic_sayalil@quicinc.com> <20250619070224.23428-2-quic_sayalil@quicinc.com> From: Sayali Lokhande Message-ID: <70bb267f-ba06-2b96-dcf6-875a046f1d87@quicinc.com> Date: Wed, 2 Jul 2025 14:25:37 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.3.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=C4TpyRP+ c=1 sm=1 tr=0 ts=6864f410 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=Uk8Cs81tDJDf_XBjPLYA:9 a=i_Q9kORXkQvSbDlD:21 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: qwoh2jbI9q_2ISO1dCk7MgResB_wv59z X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzAyMDA3MiBTYWx0ZWRfX1JcNOmlH/kpq gMIbfWXTS2FJ9W+vs7iPkzGzcaZ3OCTHnT+erj0sNiomI3ZoGWspK/zhGA3bgS4c2+JJ/wvD4Il ZMdmbL1bu79nsJCQJam9PeL4tqKqsY7PcP2u6H4NSaXe/bTm2mucEfFgY6xPz90q1HC4PHuHMwY YkHT0odW8RGHhOx2tufr+O1R6jO77ySIi7IxI9prfQW2/DZ9N0mQVQAMpZEKUQWCtQwvnphZHpL 3RRXypneqBRCUZTkF5oKvYuaKaSK26UkyzZNksi+qrt2LPlFP6WWkTNw+mgKdaMqA6hw7ne1t5q ybEaQIMJHhfUpKSn9mJtULF3lbNrrDNh6yGX4IId3pgt0kHAwlqTYgz9AxUSETbAa90juNotIqT vqMQJA6vwLAmUD8ANq7oiLXy5b+krzr/BVZmaDJzGEcwJwZ3BKw7+e0PRXDLmb9357JE8dyn X-Proofpoint-GUID: qwoh2jbI9q_2ISO1dCk7MgResB_wv59z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-02_01,2025-06-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 spamscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507020072 On 6/23/2025 7:39 PM, Konrad Dybcio wrote: > On 6/19/25 9:02 AM, Sayali Lokhande wrote: >> Add eMMC support for qcs8300 board. >> >> Signed-off-by: Sayali Lokhande >> --- > It's customary to split board and SoC changes into separate commits > > [...] > >> + sdhc_1: mmc@87C4000 { > Please use lowercase hex across DT, in all places > >> + compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5"; >> + reg = <0x0 0x87C4000 0x0 0x1000>, > To make it easier to compare by eye, we tend to pad the address > values to 8 hex digits with leading zeroes, please do so as well Sure will do >> + <0x0 0x87C5000 0x0 0x1000>; >> + reg-names = "hc", >> + "cqhci"; >> + >> + interrupts = , >> + ; >> + interrupt-names = "hc_irq", >> + "pwr_irq"; >> + >> + clocks = <&gcc GCC_SDCC1_AHB_CLK>, >> + <&gcc GCC_SDCC1_APPS_CLK>, >> + <&rpmhcc RPMH_CXO_CLK>; >> + clock-names = "iface", >> + "core", >> + "xo"; >> + >> + resets = <&gcc GCC_SDCC1_BCR>; >> + >> + power-domains = <&rpmhpd RPMHPD_CX>; >> + operating-points-v2 = <&sdhc1_opp_table>; >> + iommus = <&apps_smmu 0x0 0x0>; > In case anyone's wondering, this is actually the correct value > >> + interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY >> + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; >> + interconnect-names = "sdhc-ddr", >> + "cpu-sdhc"; > [...] > >> + sdc1_state_on: sdc1-on-state { >> + clk-pins { >> + pins = "sdc1_clk"; >> + bias-disable; >> + drive-strength = <16>; > Please move bias properties under drive-strength for consistency Will do > >> + }; >> + >> + cmd-pins { >> + pins = "sdc1_cmd"; >> + bias-pull-up; >> + drive-strength = <10>; >> + }; >> + >> + data-pins { >> + pins = "sdc1_data"; >> + bias-pull-up; >> + drive-strength = <10>; >> + }; >> + >> + rclk-pins { >> + pins = "sdc1_rclk"; >> + bias-pull-down; >> + }; >> + }; >> + >> + sdc1_state_off: sdc1-off-state { >> + clk-pins { >> + pins = "sdc1_clk"; >> + bias-bus-hold; > Is bus-hold what we want here? Other platforms do a pull-up/down > or disable bias altogether Yes we want bias-bus-hold, same as other qc platforms for example like sc7280.dtsi > > Konrad