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Mon, 24 Mar 2025 07:22:00 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52O7LxIK027659 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 24 Mar 2025 07:21:59 GMT Received: from [10.233.19.224] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 24 Mar 2025 00:21:56 -0700 Message-ID: <70db6155-a230-4f9c-a2e1-2c872c87cd39@quicinc.com> Date: Mon, 24 Mar 2025 15:21:53 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 3/3] arm64: dts: qcom: x1e80100-qcp: Add power control and sideband signals for PCIe3 To: Bryan O'Donoghue , , , , , , , , , , , , , References: <20250320055502.274849-1-quic_wenbyao@quicinc.com> <20250320055502.274849-4-quic_wenbyao@quicinc.com> <54c588be-d630-4901-8885-a042b477f168@linaro.org> Content-Language: en-US From: "Wenbin Yao (Consultant)" In-Reply-To: <54c588be-d630-4901-8885-a042b477f168@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: rSKfBKjZoSF1N6qxinMMgdaZVnSNQaYe X-Proofpoint-ORIG-GUID: rSKfBKjZoSF1N6qxinMMgdaZVnSNQaYe X-Authority-Analysis: v=2.4 cv=CPoqXQrD c=1 sm=1 tr=0 ts=67e10818 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=d_BdsECxPa-TM83sDTsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-24_03,2025-03-21_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=999 spamscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 phishscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503240052 On 3/21/2025 6:08 AM, Bryan O'Donoghue wrote: > On 20/03/2025 05:55, Wenbin Yao wrote: >> From: Qiang Yu >> >> Add perst, wake and clkreq sideband signals and required regulators in >> PCIe3 controller and PHY device tree node. Describe the voltage rails of >> the x8 PCI slots for PCIe3 port. >> >> Signed-off-by: Qiang Yu >> Signed-off-by: Wenbin Yao >> --- >>   arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 119 ++++++++++++++++++++++ >>   1 file changed, 119 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts >> b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts >> index 28086a2bc..9cd313802 100644 >> --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts >> +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts >> @@ -318,6 +318,48 @@ vreg_wcn_3p3: regulator-wcn-3p3 { >>           regulator-boot-on; >>       }; >> >> +    vreg_pcie_12v: regulator-pcie_12v { >> +        compatible = "regulator-fixed"; >> + >> +        regulator-name = "VREG_PCIE_12V"; >> +        regulator-min-microvolt = <12000000>; >> +        regulator-max-microvolt = <12000000>; >> + >> +        gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>; >> +        enable-active-high; >> + >> +        pinctrl-names = "default"; >> +        pinctrl-0 = <&pcie_x8_12v>; >> +    }; >> + >> +    vreg_pcie_3v3_aux: regulator-pcie_3v3_aux { >> +        compatible = "regulator-fixed"; >> + >> +        regulator-name = "VREG_PCIE_3P3_AUX"; >> +        regulator-min-microvolt = <3300000>; >> +        regulator-max-microvolt = <3300000>; >> + >> +        gpio = <&pmc8380_3_gpios 8 GPIO_ACTIVE_HIGH>; >> +        enable-active-high; >> + >> +        pinctrl-names = "default"; >> +        pinctrl-0 = <&pm_sde7_aux_3p3_en>; >> +    }; >> + >> +    vreg_pcie_3v3: regulator-pcie_3v3 { >> +        compatible = "regulator-fixed"; >> + >> +        regulator-name = "VREG_PCIE_3P3"; >> +        regulator-min-microvolt = <3300000>; >> +        regulator-max-microvolt = <3300000>; >> + >> +        gpio = <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>; >> +        enable-active-high; >> + >> +        pinctrl-names = "default"; >> +        pinctrl-0 = <&pm_sde7_main_3p3_en>; >> +}; >> + >>       usb-1-ss0-sbu-mux { >>           compatible = "onnn,fsusb42", "gpio-sbu-mux"; >> >> @@ -907,6 +949,60 @@ &mdss_dp3_phy { >>       status = "okay"; >>   }; >> >> +&pm8550ve_8_gpios { >> +    pcie_x8_12v: pcie-12v-default-state { >> +        pins = "gpio8"; >> +        function = "normal"; >> +        output-enable; >> +        output-high; >> +        bias-pull-down; >> +        power-source = <0>; >> +    }; >> +}; >> + >> +&pmc8380_3_gpios { >> +    pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state { >> +        pins = "gpio8"; >> +        function = "normal"; >> +        output-enable; >> +        output-high; >> +        bias-pull-down; >> +        power-source = <0>; >> +    }; >> + >> +    pm_sde7_main_3p3_en: pcie-main-3p3-default-state { >> +        pins = "gpio6"; >> +        function = "normal"; >> +        output-enable; >> +        output-high; >> +        bias-pull-down; >> +        power-source = <0>; >> +    }; >> +}; >> + >> +&pcie3 { >> + >> +    pinctrl-names = "default"; >> +    pinctrl-0 = <&pcie3_default>; >> +    perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; >> +    wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; >> +    status = "okay"; >> +}; >> + >> +&pcie3_phy { >> +    vdda-phy-supply = <&vreg_l3j_0p8>; >> +    vdda-pll-supply = <&vreg_l3e_1p2>; >> +    vdda-qref-supply = <&vreg_l3c_0p8>; >> + >> +    status = "okay"; >> +}; >> + >> +&pcie3port { >> +    vpcie12v-supply = <&vreg_pcie_12v>; >> +    vpcie3v3-supply = <&vreg_pcie_3v3>; >> +    vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>; >> +}; >> + >>   &pcie4 { >>       perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; >>       wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; >> @@ -1118,6 +1214,29 @@ nvme_reg_en: nvme-reg-en-state { >>           bias-disable; >>       }; >> >> +    pcie3_default: pcie3-default-state { >> +        clkreq-n-pins { >> +            pins = "gpio144"; >> +            function = "pcie3_clk"; >> +            drive-strength = <2>; >> +            bias-pull-up; >> +        }; >> + >> +        perst-n-pins { >> +            pins = "gpio143"; >> +            function = "gpio"; >> +            drive-strength = <2>; >> +            bias-pull-down; >> +        }; >> + >> +        wake-n-pins { >> +               pins = "gpio145"; >> +               function = "gpio"; >> +               drive-strength = <2>; >> +               bias-pull-up; >> +        }; >> +    }; >> + >>       pcie4_default: pcie4-default-state { >>           clkreq-n-pins { >>               pins = "gpio147"; >> -- >> 2.34.1 >> >> > > Recommend breaking this patch into at least two patches @ the and > > -> Add power control > -> Add sideband signals > > if your patch title requires an and its usually a good indicator of a > place to break that patch into different parts. Will fix in the next version. > > --- > bod -- With best wishes Wenbin