From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752589AbcF1UtX (ORCPT ); Tue, 28 Jun 2016 16:49:23 -0400 Received: from mx1.redhat.com ([209.132.183.28]:39346 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751017AbcF1UtV (ORCPT ); Tue, 28 Jun 2016 16:49:21 -0400 Subject: Re: [PATCH 1/5] mmu: mark spte present if the x bit is set To: Bandan Das References: <1467088360-10186-1-git-send-email-bsd@redhat.com> <1467088360-10186-2-git-send-email-bsd@redhat.com> <55601232-c941-74e8-f740-fd09e9e8a6ae@redhat.com> Cc: kvm@vger.kernel.org, guangrong.xiao@linux.intel.com, linux-kernel@vger.kernel.org From: Paolo Bonzini Message-ID: <70de38d1-2743-09dd-dc47-6242799a701c@redhat.com> Date: Tue, 28 Jun 2016 22:49:17 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Tue, 28 Jun 2016 20:49:21 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 28/06/2016 22:37, Bandan Das wrote: > Paolo Bonzini writes: > >> On 28/06/2016 19:33, Bandan Das wrote: >>>>>>> static int is_shadow_present_pte(u64 pte) >>>>>>> { >>>>>>> - return pte & PT_PRESENT_MASK && !is_mmio_spte(pte); >>>>>>> + return pte & (PT_PRESENT_MASK | shadow_x_mask) && >>>>>>> + !is_mmio_spte(pte); >>>>> >>>>> This should really be pte & 7 when using EPT. But this is okay as an >>>>> alternative to a new shadow_present_mask. >>> I could revive shadow_xonly_valid probably... Anyway, for now I will >>> add a TODO comment here. >> >> It's okay to it like this, because the only invalid PTEs reaching this >> point are those that is_mmio_spte filters away. Hence you'll never get >> -W- PTEs here, and pte & 7 is really the same as how you wrote it. It's >> pretty clever, and doesn't need a TODO at all. :) > > Thanks, understood. So, the way it is written now covers all cases for > pte & 7. Let's still add a comment - clever things are usually > confusing to many! I think another way to write it is "(pte & 0xFFFFFFFFull) && !is_mmio_spte(pte)", since non-present/non-MMIO SPTEs never use bits 1..31 (they can have non-zero bits 32..63 on 32-bit CPUs where we don't update the PTEs atomically). Guangrong, what do you prefer? Paolo