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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id h12-20020a19700c000000b004d8729d4150sm771293lfc.145.2023.02.17.12.54.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Feb 2023 12:54:14 -0800 (PST) Message-ID: <70f298cb-92a3-0bda-2192-51531a4b4f55@linaro.org> Date: Fri, 17 Feb 2023 22:54:13 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.2 Subject: Re: [PATCH v2 05/14] drm/msm/adreno: Disable has_cached_coherent for A610/A619_holi Content-Language: en-GB To: Konrad Dybcio , linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org Cc: marijn.suijten@somainline.org, Rob Clark , Abhinav Kumar , Sean Paul , David Airlie , Daniel Vetter , Akhil P Oommen , Chia-I Wu , Ricardo Ribalda , Nathan Chancellor , "Joel Fernandes (Google)" , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20230214173145.2482651-1-konrad.dybcio@linaro.org> <20230214173145.2482651-6-konrad.dybcio@linaro.org> From: Dmitry Baryshkov In-Reply-To: <20230214173145.2482651-6-konrad.dybcio@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 14/02/2023 19:31, Konrad Dybcio wrote: > These SKUs don't support the feature. Disable it to make the GPU stop > crashing after almost each and every submission - the received data on > the GPU end was simply incomplete in garbled, resulting in almost nothing > being executed properly. > > Signed-off-by: Konrad Dybcio > --- > drivers/gpu/drm/msm/adreno/adreno_device.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c > index 36f062c7582f..82757f005a1a 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c > @@ -540,7 +540,13 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) > config.rev.minor, config.rev.patchid); > > priv->is_a2xx = config.rev.core == 2; > - priv->has_cached_coherent = config.rev.core >= 6; > + > + if (config.rev.core >= 6) { > + /* Exclude A610 and A619_holi */ > + if (!(adreno_cmp_rev(ADRENO_REV(6, 1, 0, ANY_ID), config.rev) || > + adreno_cmp_rev(ADRENO_REV(6, 1, 9, 1), config.rev))) > + priv->has_cached_coherent = true; > + } I'd suggest something like: if (config.rev.core >= 6 && !(info.quirks & ADRENO_QUIRK_NO_CACHE_COHERENT)) priv->has_cache_coherent = true; Let's keep all the information and quirks in a single place. > > gpu = info->init(drm); > if (IS_ERR(gpu)) { -- With best wishes Dmitry