From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AADC934DCD2 for ; Tue, 18 Aug 2026 20:28:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787084910; cv=none; b=KLYNC8tXHGbSkyLyQQkLGTlaYy84KqPeosr2J6Iu68ErGju1esje0pABw64cnORfkzKqC9Hutg+Xe4IUT3bJceC4SGErfdNjHeyrV7p3mPzSFcdC9KlzAFmCLPG78apbSPAceDgmqfJ1dgZ4ywOFb9G7ZH634T0xZSZp0NH7PrM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787084910; c=relaxed/simple; bh=MHBq+L2kE/5yc4GSCz9uZnEJxlQ21mlHY6VxYPvkpKA=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=FGZCzJzHKHvap07WyCmvyITreBchexGmtVQ5D0urN8j8szO5NIFQwUJV0VFOnuMqslxtod3ezHFUVZ9L/XvWuuUFlo/oJTULzcRdEGU46aNlliVMHSbGtL6+RkH7CM4DXqrsJPjYS6Vna35CQMaiNR2qv2+eKXFG4BSnFbO+43M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=UYqWWWpR; dkim=pass (2048-bit key) header.d=redhat.com header.i=@redhat.com header.b=G8XT/5d2; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="UYqWWWpR"; dkim=pass (2048-bit key) header.d=redhat.com header.i=@redhat.com header.b="G8XT/5d2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1787084907; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=g7sv2BOM2TPac5OT6sZnf4rDXBLeaI6F0QDOj1pWNlY=; b=UYqWWWpR/fExVtsTpXGIk9Ni6RQIhC0sKHPrEYofPGxlEMPRwaI2iy1BDqVyQRtjjcvD/t 7xm34kx8jv5rlZExAv3GEzwa64MlF82JLMX6Xfd4sVe/wEAqtM+t5X1T+OcPfNl1M3aws6 qm90NfWr/35s2jldUy8vqekMgaDsNg0= Received: from mail-qt1-f199.google.com (mail-qt1-f199.google.com [209.85.160.199]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-400-gpst_4mMP1WTf4jwO9F_OQ-1; Tue, 18 Aug 2026 16:28:21 -0400 X-MC-Unique: gpst_4mMP1WTf4jwO9F_OQ-1 X-Mimecast-MFC-AGG-ID: gpst_4mMP1WTf4jwO9F_OQ_1787084901 Received: by mail-qt1-f199.google.com with SMTP id d75a77b69052e-5174a236220so2877021cf.3 for ; Tue, 18 Aug 2026 13:28:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=google; t=1787084900; x=1787689700; darn=vger.kernel.org; h=mime-version:user-agent:content-transfer-encoding:content-type :references:in-reply-to:date:cc:to:from:subject:message-id:from:to :cc:subject:date:message-id:reply-to:content-type; bh=g7sv2BOM2TPac5OT6sZnf4rDXBLeaI6F0QDOj1pWNlY=; b=G8XT/5d2627fmbg/x3frYJwzo5tubWrf7YWUEucrujHtC2Oz7KACxTQ5ydhL7cU+3W tgZCbfIWzrNiI5kT1vCs50l0Tec4nmWJ7RWXXQ3sNzNtCMj6vdlJoXIdTMlMK6A8v53s +HuW25OfIdXt4PCEmnzqIdAZVTBZWYxp49DBJWPTOdB77zN03GHY2SbZghh2JnM/Yw6f npHLisPPrad6O3VFlDG24FlYPKUhBtGirPZrmd4MXGu0doZ2KC3lCcwDXvVO7krMOtCE UoVFoV1Sl1U4G+i7A8u8KrjE/EWauaxnuhfszi8GF6W4JQ4Unj6bucM7RVDwIx6DY1/i xgLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787084900; x=1787689700; h=mime-version:user-agent:content-transfer-encoding:content-type :references:in-reply-to:date:cc:to:from:subject:message-id:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=g7sv2BOM2TPac5OT6sZnf4rDXBLeaI6F0QDOj1pWNlY=; b=WxCtsFdEvChnSogihTxZ8GfWuxb5LJFCF0CJ/IL2EUse0b4TQ2tOD+juPhgkjescmq n+6QWkhFRw9iTQ2pXQI7dZppJuYXjWnnQ5IdUmTzFli7pEN4FvNh7pVppYR/oSHja6Fs XiH5QTHwC/ONX00+vlPXnRWiJflkqmi1C8Q0JnrKfli9Ij4cZTh43dDKXQekpM7q3ZHJ VwS5MEmUVWgOfSWLw/65ge+LNbmWfUxeMgn/qEwa8MFEK/4sh9+KKuYHCZHz/1YFQzj/ 9galfUbOAVlrg4vVjYFU2FP1Ec167sy+PqHfSxWnosEeexuUlhhGD3IVreLhK4nKE12O S7/Q== X-Gm-Message-State: AOJu0Yz1ceCZ9oaW0csNuoRCW5v/33ep3x3Y0Vvda75J5feWYBBN3gOK JfXuCymlguYitYIql6bYeAKmyF4OIDTPHzH5AZlpWnFPHvVtUkYvMJ8WHbmQHp91ONj4usANSrs AaLChX2/umbGIibi2aZlTkfT493dDiR3aGL6My1yLPScwZYOncLTItz94yNHbJtSRHg== X-Gm-Gg: AR+sD12M/mwpfWJsOtfyNnAnjtc0rJlqdR3aNnuxx2AcQUN9X2v1xb7jet/GCiX+faR h/ioERzMleKneRXScLewHTe5d1WejLK/scmj1R7BMX6YA47zFRIrmmZ3zXubtUG7dqjh3hmyDwD k2zHi+Nhdksrs42vhA2lwMzLKhl8i6aA8rDn22Cv/Gdrs2IB+apOK92HAYSOk+THCuQcfWsRSDP iX0iAhUzeJ1fKtEY5t3A0/thPpudXE5HmAoYQ8N2/I+behkSLS4pQrpl5Vow7nONM6PpHu00Hr5 HpYuj0heQAUKh7+IGx100gtgBVb5cvGAMcZWKF82yamR9ajt3qL2y7nKMStTa7ZowhdXAkiz X-Received: by 2002:a05:622a:1a99:b0:51b:fe30:b8da with SMTP id d75a77b69052e-52dd32cc365mr7489601cf.33.1787084900600; Tue, 18 Aug 2026 13:28:20 -0700 (PDT) X-Received: by 2002:a05:622a:1a99:b0:51b:fe30:b8da with SMTP id d75a77b69052e-52dd32cc365mr7488991cf.33.1787084900104; Tue, 18 Aug 2026 13:28:20 -0700 (PDT) Received: from [192.168.8.4] ([100.0.180.93]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-52db60eb025sm47437921cf.5.2026.08.18.13.28.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Aug 2026 13:28:19 -0700 (PDT) Message-ID: <70ff3bb7914899d845e884eea00b47621d295e3a.camel@redhat.com> Subject: Re: [PATCH v4 1/2] drm/nouveau/pci: use config-space MSI rearm on MCP79/MCP7A (NVAC) From: lyude@redhat.com To: Marek Czernohous , nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org, Danilo Krummrich , David Airlie , Simona Vetter Date: Tue, 18 Aug 2026 16:28:19 -0400 In-Reply-To: <178688574401.522643.12812428444459119913@gmail.com> References: <178688574400.522643.6695278742335367229@gmail.com> <178688574401.522643.12812428444459119913@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.3 (3.58.3-1.fc43) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Reviewed-by: Lyude Paul On Sun, 2026-08-16 at 15:09 +0200, Marek Czernohous wrote: > From: Marek Czernohous >=20 > NVAC (MCP79/MCP7A) uses g94_pci_func, whose .msi_rearm is > nv40_pci_msi_rearm(): a re-arm write through the MMIO mirror of PCI > config space.=C2=A0 On this IGP that path is unreliable; when a re-arm is > missed the interrupt line stays dead, command submission times out > and > the GPU appears hung until reboot.=C2=A0 On an Apple Mac mini (early 2009= , > MCP79, boot0 0x0ac080b1) this showed as sporadic fifo timeouts and > GPU > hangs under load unless MSI was disabled via config=3DNvMSI=3D0. >=20 > Give NVAC its own pci func that re-arms through real PCI config space > (nv46_pci_msi_rearm) instead.=C2=A0 This follows existing precedent: > nv46.c > documents the MMIO-mirror re-arm as broken on several related parts, > and commit 5112abc6a433 ("drm/nouveau/pci/g92: Fix rearm") fixed g92 > the same way while moving the remaining chipsets, NVAC included, into > the newly added shared g94 table, where NVAC stayed on the MMIO path. > This change completes that fix for NVAC.=C2=A0 The sibling IGP NVAA > (MCP77/MCP78) has MSI disabled entirely as "reported broken" in > nvkm_pci_new_(); NVAC works correctly once the re-arm goes through > config space, so disabling MSI is not necessary. >=20 > Only NVAC is switched: that is the hardware this has been validated > on.=C2=A0 The other users of g94_pci_func (G94/G96/G98/GT2xx and the > MCP77/MCP89 IGPs) keep their current behavior; MCP77 and MCP89 > plausibly want the same treatment but were not tested. >=20 > Tested on the Mac mini as a daily driver for two months with MSI > enabled and zero fifo timeouts.=C2=A0 Independently confirmed stable on a= n > iMac9,1 (MCP79) running 6.12.90 with the v1 form of this change (the > same one-line functional switch, applied to that kernel's g94 > implementation). >=20 > Fixes: 5112abc6a433 ("drm/nouveau/pci/g92: Fix rearm") > Cc: # v6.16+ > Tested-by: Fab Stz > Assisted-by: Claude:claude-opus-4-7 > Assisted-by: Claude:claude-opus-4-8 > Signed-off-by: Marek Czernohous > --- > =C2=A0.../gpu/drm/nouveau/include/nvkm/subdev/pci.h |=C2=A0 1 + > =C2=A0.../gpu/drm/nouveau/nvkm/engine/device/base.c |=C2=A0 2 +- > =C2=A0.../gpu/drm/nouveau/nvkm/subdev/pci/Kbuild=C2=A0=C2=A0=C2=A0 |=C2= =A0 1 + > =C2=A0.../gpu/drm/nouveau/nvkm/subdev/pci/mcp79.c=C2=A0=C2=A0 | 35 > +++++++++++++++++++ > =C2=A04 files changed, 38 insertions(+), 1 deletion(-) > =C2=A0create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pci/mcp79.c >=20 > diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h > b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h > index 112b674ed9c8..0172e0d200f8 100644 > --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h > +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h > @@ -46,6 +46,7 @@ int nv4c_pci_new(struct nvkm_device *, enum > nvkm_subdev_type, int inst, struct n > =C2=A0int g84_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int > inst, struct nvkm_pci **); > =C2=A0int g92_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int > inst, struct nvkm_pci **); > =C2=A0int g94_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int > inst, struct nvkm_pci **); > +int mcp79_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int > inst, struct nvkm_pci **); > =C2=A0int gf100_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int > inst, struct nvkm_pci **); > =C2=A0int gf106_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int > inst, struct nvkm_pci **); > =C2=A0int gk104_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int > inst, struct nvkm_pci **); > diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c > b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c > index ea62dc97f118..f7e02a16e5bc 100644 > --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c > +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c > @@ -1237,7 +1237,7 @@ nvac_chipset =3D { > =C2=A0 .mc=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D { 0x00000001, g98_mc_n= ew }, > =C2=A0 .mmu=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D { 0x00000001, mcp77_mmu_new= }, > =C2=A0 .mxm=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D { 0x00000001, nv50_mxm_new = }, > - .pci=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D { 0x00000001, g94_pci_new }, > + .pci=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D { 0x00000001, mcp79_pci_new }, > =C2=A0 .therm=C2=A0=C2=A0=C2=A0 =3D { 0x00000001, g84_therm_new }, > =C2=A0 .timer=C2=A0=C2=A0=C2=A0 =3D { 0x00000001, nv41_timer_new }, > =C2=A0 .volt=C2=A0=C2=A0=C2=A0=C2=A0 =3D { 0x00000001, nv40_volt_new }, > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild > b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild > index a14ea0f7b1c8..90f03baeb22a 100644 > --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild > +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild > @@ -9,6 +9,7 @@ nvkm-y +=3D nvkm/subdev/pci/nv4c.o > =C2=A0nvkm-y +=3D nvkm/subdev/pci/g84.o > =C2=A0nvkm-y +=3D nvkm/subdev/pci/g92.o > =C2=A0nvkm-y +=3D nvkm/subdev/pci/g94.o > +nvkm-y +=3D nvkm/subdev/pci/mcp79.o > =C2=A0nvkm-y +=3D nvkm/subdev/pci/gf100.o > =C2=A0nvkm-y +=3D nvkm/subdev/pci/gf106.o > =C2=A0nvkm-y +=3D nvkm/subdev/pci/gk104.o > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/mcp79.c > b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/mcp79.c > new file mode 100644 > index 000000000000..e2ae242f1aa7 > --- /dev/null > +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/mcp79.c > @@ -0,0 +1,35 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright 2026 Marek Czernohous > + * > + * MCP79/MCP7A (NVAC): like g94, but MSI re-arm goes through real > PCI > + * config space.=C2=A0 The MMIO-mirror re-arm is unreliable on this IGP > and a > + * missed re-arm kills the interrupt line (see the nv46 comment; g92 > + * already re-arms through config space for the same reason). > + */ > +#include "priv.h" > + > +static const struct nvkm_pci_func > +mcp79_pci_func =3D { > + .cfg =3D { .addr =3D 0x088000, .size =3D 0x1000 }, > + > + .init =3D g84_pci_init, > + .msi_rearm =3D nv46_pci_msi_rearm, > + > + .pcie.init =3D g84_pcie_init, > + .pcie.set_link =3D g84_pcie_set_link, > + > + .pcie.max_speed =3D g84_pcie_max_speed, > + .pcie.cur_speed =3D g84_pcie_cur_speed, > + > + .pcie.set_version =3D g84_pcie_set_version, > + .pcie.version =3D g84_pcie_version, > + .pcie.version_supported =3D g92_pcie_version_supported, > +}; > + > +int > +mcp79_pci_new(struct nvkm_device *device, enum nvkm_subdev_type > type, int inst, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 struct nvkm_pci **ppci) > +{ > + return nvkm_pci_new_(&mcp79_pci_func, device, type, inst, > ppci); > +}