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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa625e4db6csm114422066b.39.2024.12.05.08.40.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Dec 2024 08:40:18 -0800 (PST) Message-ID: <710aa948-d27f-49f6-a4a8-73f6208502c3@oss.qualcomm.com> Date: Thu, 5 Dec 2024 17:40:15 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/6] phy: qcom: Introduce PCIe UNIPHY 28LP driver To: Varadarajan Narayanan , lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org, andersson@kernel.org, konradybcio@kernel.org, p.zabel@pengutronix.de, quic_nsekar@quicinc.com, dmitry.baryshkov@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org References: <20241204113329.3195627-1-quic_varada@quicinc.com> <20241204113329.3195627-3-quic_varada@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241204113329.3195627-3-quic_varada@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 49cBHjS-TPfY6mj8WTb_71kaohBzuEpY X-Proofpoint-ORIG-GUID: 49cBHjS-TPfY6mj8WTb_71kaohBzuEpY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 mlxlogscore=999 phishscore=0 malwarescore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412050121 On 4.12.2024 12:33 PM, Varadarajan Narayanan wrote: > From: Nitheesh Sekar > > Add Qualcomm PCIe UNIPHY 28LP driver support present > in Qualcomm IPQ5332 SoC and the phy init sequence. > > Signed-off-by: Nitheesh Sekar > Signed-off-by: Varadarajan Narayanan > --- [...] > +struct qcom_uniphy_pcie_regs { > + unsigned int offset; > + unsigned int val; u32 > +}; > + > +struct qcom_uniphy_pcie_data { > + int lanes; > + /* 2nd lane offset */ > + int lane_offset; 'lanes', 'lane_offset' and '2nd lane' together imply one of: - there can be more lines, all at an equal offset - there can only ever be two lines Please specify which one is the case > + unsigned int phy_type; > + const struct qcom_uniphy_pcie_regs *init_seq; > + unsigned int init_seq_num; > + unsigned int pipe_clk_rate; > +}; > + > +struct qcom_uniphy_pcie { > + struct phy phy; > + struct device *dev; > + const struct qcom_uniphy_pcie_data *data; > + struct clk_bulk_data *clks; > + int num_clks; > + struct reset_control *resets; > + void __iomem *base; > +}; > + > +#define phy_to_dw_phy(x) container_of((x), struct qca_uni_pcie_phy, phy) A space after #define, please > + > +static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = { > + { > + .offset = PHY_CFG_PLLCFG, > + .val = 0x30, > + }, { > + .offset = PHY_CFG_EIOS_DTCT_REG, > + .val = 0x53ef, > + }, { > + .offset = PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME, > + .val = 0xCf, mixed case hex.. please make it lowercase > + }, > +}; > + > +static const struct qcom_uniphy_pcie_data ipq5332_x1_data = { > + .lanes = 1, > + .phy_type = PHY_TYPE_PCIE_GEN3, > + .init_seq = ipq5332_regs, > + .init_seq_num = ARRAY_SIZE(ipq5332_regs), > + .pipe_clk_rate = 250000000, > +}; > + > +static const struct qcom_uniphy_pcie_data ipq5332_x2_data = { > + .lanes = 2, > + .lane_offset = 0x800, > + .phy_type = PHY_TYPE_PCIE_GEN3, > + .init_seq = ipq5332_regs, > + .init_seq_num = ARRAY_SIZE(ipq5332_regs), > + .pipe_clk_rate = 250000000, > +}; Are there going to be more UNIPHY-equipped SoCs? > + > +static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy) > +{ > + const struct qcom_uniphy_pcie_data *data = phy->data; > + const struct qcom_uniphy_pcie_regs *init_seq; > + void __iomem *base = phy->base; > + int lane, i; > + > + for (lane = 0; lane != data->lanes; lane++) { while effectively the same, < would be less eyebrow-raising > + init_seq = data->init_seq; > + > + for (i = 0; i < data->init_seq_num; i++, init_seq++) > + writel(init_seq->val, base + init_seq->offset); writel(init_seq[i].val, ...) > + > + base += data->lane_offset; > + } > +} > + > +static int qcom_uniphy_pcie_power_off(struct phy *x) > +{ > + struct qcom_uniphy_pcie *phy = phy_get_drvdata(x); > + > + clk_bulk_disable_unprepare(phy->num_clks, phy->clks); > + > + reset_control_assert(phy->resets); This can fail, return it instead of zero [...] > +MODULE_LICENSE("Dual BSD/GPL"); I think this is too vague, there are many BSD variants Konrad