From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3290C43214 for ; Mon, 9 Aug 2021 10:55:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A3BC9610CF for ; Mon, 9 Aug 2021 10:55:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234802AbhHIK4F (ORCPT ); Mon, 9 Aug 2021 06:56:05 -0400 Received: from smtp-relay-canonical-1.canonical.com ([185.125.188.121]:41324 "EHLO smtp-relay-canonical-1.canonical.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234112AbhHIK4C (ORCPT ); Mon, 9 Aug 2021 06:56:02 -0400 Received: from mail-ed1-f71.google.com (mail-ed1-f71.google.com [209.85.208.71]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-canonical-1.canonical.com (Postfix) with ESMTPS id 000B74064A for ; Mon, 9 Aug 2021 10:55:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1628506542; bh=0/QQ7GCmzFb/lwnEgdDUeVfna7ZuR+UkebHo1Vz0Gqw=; h=Subject:To:Cc:References:From:Message-ID:Date:MIME-Version: In-Reply-To:Content-Type; b=JNv5OZ52eBn7Z9PLrUTmfvh1mpKL3kb8KV5BiSg4gAcPl6W72WfoHe4GC+i0z5bH0 bB6s2PlSQ7NkLyfMzv5BBVe+Hjx2bqmJ0+pSG3CC79Hwj71TdVQqOT6F7bqiQoTAZj yo1NFQ8eej/pmu4Ogi9rGi9F424+sbtZQjWNm+p3EIe0ZQKjXQJQvhZHKHSuOxbvWV ILUQj2EPjSNbmPq6IbmazBNYmrqHOqa3a6IdaylTlOVC7EWMNQGFn50pIY+2xdvfId mpNUcWwpyuh0LBMIaEK0MXA58g52hTVZYvdsYeIpUqmsTGKnkigoQRx8hamQ6/+H24 DQLOLzDJXvGvw== Received: by mail-ed1-f71.google.com with SMTP id cm18-20020a0564020c92b02903bc7f21d540so8686852edb.13 for ; Mon, 09 Aug 2021 03:55:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=0/QQ7GCmzFb/lwnEgdDUeVfna7ZuR+UkebHo1Vz0Gqw=; b=kjua8BR8z0Au1tIg3Mt4MhKRP65GRohc7jhqln65Vb0Mag2XvBjGSaxJWAIxb6psOG /7Vs7r5L03vxILYKoQxVxEZqs8HhZqWmqanuc0DnmrGAZ5PZ7A0LA8yio7NetM7h9wS8 sHAPqHQNrd/kv9n65HFGRKQWOLHJtzhooughV9i3zFyspI5Ul45RamMNT/hJnjLHEeSy hAx+XvG/L0kcunbom6u7AqsneEQNgGtcNXCD09/s9dpFwNZim00LwEq69nlr/3Em/5tT bEmxZHAyJ/cdreXPdxSBN77wLA1aGdeVuzsVyDiL/7JdJzAYWb8ulpItinYik+F02lLR gUgw== X-Gm-Message-State: AOAM531CYyRXMP6P0il3V9lgJkaEagu8TIaYYcVsY0istOj8gPtTSc6Q DuHQE/V0nH6RTHefeGFlFPDsYjpxAeC6rC9a2k/nTYMjeBdDyeJl/AUyxP8u7QGSz0GVqpIq4XO Bc6dgvbIqwrCPq2tnCgA03trUsqHspvUnEtRyrsavsw== X-Received: by 2002:a17:906:1b54:: with SMTP id p20mr404470ejg.395.1628506530735; Mon, 09 Aug 2021 03:55:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxUplgKeUyXmIIles2EuYZDpGS9skc6nxGXUAbVQyS+5moWpAWS0mJjpD2RuM252XF4XwBPcA== X-Received: by 2002:a17:906:1b54:: with SMTP id p20mr404451ejg.395.1628506530585; Mon, 09 Aug 2021 03:55:30 -0700 (PDT) Received: from [192.168.8.102] ([86.32.42.198]) by smtp.gmail.com with ESMTPSA id b5sm5798891ejq.56.2021.08.09.03.55.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Aug 2021 03:55:29 -0700 (PDT) Subject: Re: [PATCH v2 7/8] clk: samsung: Add Exynos850 clock driver stub To: Sam Protsenko , Sylwester Nawrocki , Chanwoo Choi , Linus Walleij , Tomasz Figa , =?UTF-8?Q?Pawe=c5=82_Chmiel?= Cc: Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org References: <20210806152146.16107-1-semen.protsenko@linaro.org> <20210806152146.16107-8-semen.protsenko@linaro.org> From: Krzysztof Kozlowski Message-ID: <7110b1e2-1aee-6ddf-803f-ee392e494f2d@canonical.com> Date: Mon, 9 Aug 2021 12:55:27 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210806152146.16107-8-semen.protsenko@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/08/2021 17:21, Sam Protsenko wrote: > For now it's just a stub driver to make the serial driver work. Later it > will be implemented properly. This driver doesn't really change clocks, > only registers the UART clock as a fixed-rate clock. Without this clock > driver the UART driver won't work, as it's trying to obtain "uart" clock > and fails if it's not able to. You know that as temporary solution you can add necessary clocks directly in your DTS as fixed-rate-clocks? Effect would be quite similar to the one here for UART driver but instead adding some temporary code you would add temporary DTS nodes and references. I am fine with this approach although the binding (if ever defined...) would need to be marked as experimental. > > In order to get a functional serial console we have to implement that > minimal clock driver with "uart" clock. It's not necessary to actually > configure clocks, as those are already configured in bootloader, so > kernel can rely on that for now. > > Signed-off-by: Sam Protsenko > --- > Changes in v2: > - Used hard coded clock indexes, as clock bindings were removed; will > add clock bindings back (reimplemented) once proper clock driver is > ready > - Removed .data = 0 for exynos850-oscclk, as it's in BSS section > - Removed comma for terminator {} > - Made exynos850_clk_init() static > - Removed checking np for NULL, as it's already done in of_iomap() > > drivers/clk/samsung/Makefile | 1 + > drivers/clk/samsung/clk-exynos850.c | 64 +++++++++++++++++++++++++++++ > 2 files changed, 65 insertions(+) > create mode 100644 drivers/clk/samsung/clk-exynos850.c > > diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile > index 028b2e27a37e..c46cf11e4d0b 100644 > --- a/drivers/clk/samsung/Makefile > +++ b/drivers/clk/samsung/Makefile > @@ -17,6 +17,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o > obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o > obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o > +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o > obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o > obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o > obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o > diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c > new file mode 100644 > index 000000000000..36c7c7fe7cf0 > --- /dev/null > +++ b/drivers/clk/samsung/clk-exynos850.c > @@ -0,0 +1,64 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2019 Samsung Electronics Co., Ltd. > + * Copyright (C) 2021 Linaro Ltd. > + * > + * Common Clock Framework support for Exynos850 SoC. > + */ > + > +#include > +#include > +#include > +#include > +#include > + > +#include "clk.h" > + > +/* Will be extracted to bindings header once proper clk driver is implemented */ > +#define OSCCLK 1 > +#define DOUT_UART 2 > +#define CLK_NR_CLKS 3 > + > +/* Fixed rate clocks generated outside the SoC */ > +static struct samsung_fixed_rate_clock exynos850_fixed_rate_ext_clks[] __initdata = { > + FRATE(OSCCLK, "fin_pll", NULL, 0, 26000000), > +}; > + > +/* > + * Model the UART clock as a fixed-rate clock for now, to make serial driver > + * work. This clock is already configured in the bootloader. > + */ > +static const struct samsung_fixed_rate_clock exynos850_peri_clks[] __initconst = { > + FRATE(DOUT_UART, "DOUT_UART", NULL, 0, 200000000), > +}; > + > +static const struct of_device_id ext_clk_match[] __initconst = { > + { .compatible = "samsung,exynos850-oscclk" }, > + {} > +}; > + > +static void __init exynos850_clk_init(struct device_node *np) > +{ > + void __iomem *reg_base; > + struct samsung_clk_provider *ctx; > + > + reg_base = of_iomap(np, 0); > + if (!reg_base) > + panic("%s: failed to map registers\n", __func__); > + > + ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); > + if (!ctx) > + panic("%s: unable to allocate ctx\n", __func__); Not needed, the samsung_clk_init() panics or returns valid memory. > + > + samsung_clk_of_register_fixed_ext(ctx, > + exynos850_fixed_rate_ext_clks, > + ARRAY_SIZE(exynos850_fixed_rate_ext_clks), > + ext_clk_match); > + > + samsung_clk_register_fixed_rate(ctx, exynos850_peri_clks, > + ARRAY_SIZE(exynos850_peri_clks)); > + > + samsung_clk_of_add_provider(np, ctx); > +} > + > +CLK_OF_DECLARE(exynos850_clk, "samsung,exynos850-clock", exynos850_clk_init); > Best regards, Krzysztof