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Fri, 21 Jun 2024 10:21:06 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 21 Jun 2024 10:21:06 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jun 2024 10:21:06 -0500 Received: from [172.24.227.94] (uda0132425.dhcp.ti.com [172.24.227.94]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45LFL2re072209; Fri, 21 Jun 2024 10:21:03 -0500 Message-ID: <71126a8f-7a6d-4561-bb13-a403fe580ab2@ti.com> Date: Fri, 21 Jun 2024 20:51:02 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: ti: k3-j784s4-main: Add node for EHRPWMs To: Udit Kumar , CC: , , , , , , , Dasnavis Sabiya References: <20240603112938.2188510-1-u-kumar1@ti.com> From: Vignesh Raghavendra Content-Language: en-US In-Reply-To: <20240603112938.2188510-1-u-kumar1@ti.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 On 03/06/24 16:59, Udit Kumar wrote: > From: Dasnavis Sabiya > > Add dts nodes for 6 EHRPWM instances on SoC. > > Signed-off-by: Dasnavis Sabiya > Signed-off-by: Udit Kumar > --- > arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 66 ++++++++++++++++++++++ > 1 file changed, 66 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > index 6a4554c6c9c1..f6fc2ce55f9b 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > @@ -75,6 +75,72 @@ serdes_ln_ctrl: mux-controller@4080 { > , > ; > }; > + > + ehrpwm_tbclk: clock-controller@4140 { > + compatible = "ti,am654-ehrpwm-tbclk"; > + reg = <0x4140 0x18>; > + #clock-cells = <1>; > + }; > + }; > + > + main_ehrpwm0: pwm@3000000 { > + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; > + #pwm-cells = <3>; This needs to be ordered as per https://www.kernel.org/doc/Documentation/devicetree/bindings/dts-coding-style.rst (compatible is immediately followed by reg) Will fix all the nodes locally before merging > + reg = <0x00 0x3000000 0x00 0x100>; > + clocks = <&ehrpwm_tbclk 0>, <&k3_clks 219 0>; > + clock-names = "tbclk", "fck"; > + power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; > + status = "disabled"; > + }; > + > + main_ehrpwm1: pwm@3010000 { > + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; > + #pwm-cells = <3>; > + reg = <0x00 0x3010000 0x00 0x100>; > + clocks = <&ehrpwm_tbclk 1>, <&k3_clks 220 0>; > + clock-names = "tbclk", "fck"; > + power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; > + status = "disabled"; > + }; > + > + main_ehrpwm2: pwm@3020000 { > + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; > + #pwm-cells = <3>; > + reg = <0x00 0x3020000 0x00 0x100>; > + clocks = <&ehrpwm_tbclk 2>, <&k3_clks 221 0>; > + clock-names = "tbclk", "fck"; > + power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; > + status = "disabled"; > + }; > + > + main_ehrpwm3: pwm@3030000 { > + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; > + #pwm-cells = <3>; > + reg = <0x00 0x3030000 0x00 0x100>; > + clocks = <&ehrpwm_tbclk 3>, <&k3_clks 222 0>; > + clock-names = "tbclk", "fck"; > + power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; > + status = "disabled"; > + }; > + > + main_ehrpwm4: pwm@3040000 { > + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; > + #pwm-cells = <3>; > + reg = <0x00 0x3040000 0x00 0x100>; > + clocks = <&ehrpwm_tbclk 4>, <&k3_clks 223 0>; > + clock-names = "tbclk", "fck"; > + power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; > + status = "disabled"; > + }; > + > + main_ehrpwm5: pwm@3050000 { > + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; > + #pwm-cells = <3>; > + reg = <0x00 0x3050000 0x00 0x100>; > + clocks = <&ehrpwm_tbclk 5>, <&k3_clks 224 0>; > + clock-names = "tbclk", "fck"; > + power-domains = <&k3_pds 224 TI_SCI_PD_EXCLUSIVE>; > + status = "disabled"; > }; > > gic500: interrupt-controller@1800000 { -- Regards Vignesh