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Wed, 24 Apr 2024 07:59:31 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 43O7xTRu032237 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 24 Apr 2024 07:59:29 GMT Received: from [10.216.52.243] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 24 Apr 2024 00:59:24 -0700 Message-ID: <7122785c-d6cf-4425-82a5-2f65e0a523d9@quicinc.com> Date: Wed, 24 Apr 2024 13:29:21 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1] arm64: dts: qcom: sc7280: Remove CTS/RTS configuration Content-Language: en-US To: Luca Weiss , , , , , , , , , , , , , CC: , References: <20240416105650.2626-1-quic_vdadhani@quicinc.com> From: Viken Dadhaniya In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: GCUW2iiJ6IpqGcnBnV84AUMZ8aKdrkGj X-Proofpoint-GUID: GCUW2iiJ6IpqGcnBnV84AUMZ8aKdrkGj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-04-24_05,2024-04-23_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 phishscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 adultscore=0 clxscore=1015 malwarescore=0 impostorscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404240034 On 4/16/2024 5:08 PM, Luca Weiss wrote: > On Tue Apr 16, 2024 at 12:56 PM CEST, Viken Dadhaniya wrote: >> Remove CTS and RTS pinctrl configuration for UART5 node as >> it's designed for debug UART for all the board variants of the >> sc7280 chipset. >> >> Also change compatible string to debug UART. > > This change has little to do with the SoC design though and is dependent > on the usage on a given board, right? Also the QCM6490 datasheet > mentions gpio21 & gpio22 can be used for UART_CTS and UART_RFR. > > But at least consistency-wise this change makes sense, in practically > all other SoCs one UART is marked as geni-debug-uart. > > But with this patch you should then also remove some overrides that are > placed in various boards already? > > arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts: compatible = "qcom,geni-debug-uart"; > arch/arm64/boot/dts/qcom/qcm6490-idp.dts: compatible = "qcom,geni-debug-uart"; > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts: compatible = "qcom,geni-debug-uart"; > arch/arm64/boot/dts/qcom/sc7280-idp.dtsi: compatible = "qcom,geni-debug-uart"; > arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi: compatible = "qcom,geni-debug-uart"; > > Regards > Luca > Updated in V2. >> >> Fixes: 38cd93f413fd ("arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node") >> Signed-off-by: Viken Dadhaniya >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++------------ >> 1 file changed, 2 insertions(+), 12 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 38c183b2bb26..2a6b4c4639d1 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -1440,12 +1440,12 @@ >> }; >> >> uart5: serial@994000 { >> - compatible = "qcom,geni-uart"; >> + compatible = "qcom,geni-debug-uart"; >> reg = <0 0x00994000 0 0x4000>; >> clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; >> clock-names = "se"; >> pinctrl-names = "default"; >> - pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; >> + pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; >> interrupts = ; >> power-domains = <&rpmhpd SC7280_CX>; >> operating-points-v2 = <&qup_opp_table>; >> @@ -5397,16 +5397,6 @@ >> function = "qup04"; >> }; >> >> - qup_uart5_cts: qup-uart5-cts-state { >> - pins = "gpio20"; >> - function = "qup05"; >> - }; >> - >> - qup_uart5_rts: qup-uart5-rts-state { >> - pins = "gpio21"; >> - function = "qup05"; >> - }; >> - >> qup_uart5_tx: qup-uart5-tx-state { >> pins = "gpio22"; >> function = "qup05"; >