From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D577D500941; Sat, 17 Jan 2026 19:34:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768678451; cv=none; b=N5qWgqlNQgyGMZ8GHzEM3/yM85WHTscAXwGSNIpoE6Bp2GHk1NzyxunbNHSxRK1bZTIv7qnUApzWEmJkOjq2WCUpLXdvQQ3dEGwNyPuIyfrdZGEpT1xz/dUlyvDfa1GChwdScq0hYB8DQYAeYWbqt+uEDTkNpW2TJHrvfFYOpOc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768678451; c=relaxed/simple; bh=wpTWkJGvYGgIrpy42NJCYhFMaIKGWMQ+XWrCorWm23U=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=iidC4jGljjhaGf33R0RM2/hZe6CjKLGIkKGVDnDp7P1WFq1QVeFLXxf/fLs22x9X0mQkMzDVBspSmtT4S9HIG7UXtBHdk3roCr2YIhgL62LX0DNY+zSbBW8VP29kEA3MTj2iKA3oBF3iyBRDGcAleK0tLlrV9836QUiyx3ozx7I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=c87TgsZn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="c87TgsZn" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 967C2C4CEF7; Sat, 17 Jan 2026 19:34:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768678451; bh=wpTWkJGvYGgIrpy42NJCYhFMaIKGWMQ+XWrCorWm23U=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=c87TgsZnxv91omHR1/+s/6glC0pJAypxidGktSrOwJ5OXRRG40jvcC47U1c25aMqd cWxUI4dgQSuDPU5GxEYGKdOzYxYfvMXFjFEPuFY5Rd8d+uTIYJj/6lmw6nGgnLNisR Fhb9bwG803zsH/c3jxuUaALQ7N7w635HehLXJ2hp9Q6oHVTQTF3LAAu8rMNdrfnLPu G1Zf0NAESCNQIhRBedkxDwxldA3JqKekDR3ePoj9tWINTrLhacX1BfoMXxa2P4FqAz r2GHjqOVVpTcdS2tiNxQl0w67OyNXA0Vk4MKwmzQVcF5TsvWAD5IY5f6O3dus8dXcy P5RvnNFpKX6og== Message-ID: <7145bbaa-17fa-4b36-88c9-44eb0dacf83d@kernel.org> Date: Sat, 17 Jan 2026 20:34:05 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/5] arm64: dts: exynos: gs101: add cmu_dpu and sysreg_dpu dt nodes To: Peter Griffin , =?UTF-8?Q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel-team@android.com, Will McVicker , Juan Yescas , Doug Anderson References: <20260113-dpu-clocks-v3-0-cb85424f2c72@linaro.org> <20260113-dpu-clocks-v3-5-cb85424f2c72@linaro.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 13/01/2026 11:59, Peter Griffin wrote: > Enable the cmu_dpu clock management unit. It feeds some of the display > IPs. Additionally add the sysreg_dpu node which contains the > BUSCOMPONENT_DRCG_EN and MEMCLK registers required by cmu_dpu to enable > dynamic root clock gating of bus components. > > Reviewed-by: André Draszik > Signed-off-by: Peter Griffin > --- > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > Thanks, applied. It is however very late in the cycle, so there is a chance this will miss the merge window. If this happens, I will keep it for the next cycle (no need for resending). Best regards, Krzysztof