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[82.81.161.50]) by smtp.gmail.com with ESMTPSA id q13-20020a05620a2a4d00b006b5763bffebsm10485498qkp.34.2022.07.18.02.38.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 02:38:49 -0700 (PDT) Message-ID: <71585b6bfd584bf01b09d898c5702a8ab54b5308.camel@redhat.com> Subject: Re: [PATCH] KVM: SVM: Fix x2APIC MSRs interception From: Maxim Levitsky To: Suravee Suthikulpanit , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, jon.grimm@amd.com Date: Mon, 18 Jul 2022 12:38:47 +0300 In-Reply-To: <20220718083833.222117-1-suravee.suthikulpanit@amd.com> References: <20220718083833.222117-1-suravee.suthikulpanit@amd.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.40.4 (3.40.4-5.fc34) MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2022-07-18 at 03:38 -0500, Suravee Suthikulpanit wrote: > The index for svm_direct_access_msrs was incorrectly initialized with > the APIC MMIO register macros. Fix by introducing a macro for calculating > x2APIC MSRs. > > Fixes: 5c127c85472c ("KVM: SVM: Adding support for configuring x2APIC MSRs interception") > Cc: Maxim Levitsky > Signed-off-by: Suravee Suthikulpanit > --- >  arch/x86/kvm/svm/svm.c | 52 ++++++++++++++++++++++-------------------- >  1 file changed, 27 insertions(+), 25 deletions(-) > > diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c > index ba81a7e58f75..aef63aae922d 100644 > --- a/arch/x86/kvm/svm/svm.c > +++ b/arch/x86/kvm/svm/svm.c > @@ -74,6 +74,8 @@ static uint64_t osvw_len = 4, osvw_status; >   >  static DEFINE_PER_CPU(u64, current_tsc_ratio); >   > +#define X2APIC_MSR(x)  (APIC_BASE_MSR + (x >> 4)) > + >  static const struct svm_direct_access_msrs { >         u32 index;   /* Index of the MSR */ >         bool always; /* True if intercept is initially cleared */ > @@ -100,31 +102,31 @@ static const struct svm_direct_access_msrs { >         { .index = MSR_IA32_CR_PAT,                     .always = false }, >         { .index = MSR_AMD64_SEV_ES_GHCB,               .always = true  }, >         { .index = MSR_TSC_AUX,                         .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_ID),           .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_LVR),          .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_TASKPRI),      .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_ARBPRI),       .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_PROCPRI),      .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_EOI),          .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_RRR),          .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_LDR),          .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_DFR),          .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_SPIV),         .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_ISR),          .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_TMR),          .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_IRR),          .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_ESR),          .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_ICR),          .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_ICR2),         .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_LVTT),         .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_LVTTHMR),      .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_LVTPC),        .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_LVT0),         .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_LVT1),         .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_LVTERR),       .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_TMICT),        .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_TMCCT),        .always = false }, > -       { .index = (APIC_BASE_MSR + APIC_TDCR),         .always = false }, > +       { .index = X2APIC_MSR(APIC_ID),                 .always = false }, > +       { .index = X2APIC_MSR(APIC_LVR),                .always = false }, > +       { .index = X2APIC_MSR(APIC_TASKPRI),            .always = false }, > +       { .index = X2APIC_MSR(APIC_ARBPRI),             .always = false }, > +       { .index = X2APIC_MSR(APIC_PROCPRI),            .always = false }, > +       { .index = X2APIC_MSR(APIC_EOI),                .always = false }, > +       { .index = X2APIC_MSR(APIC_RRR),                .always = false }, > +       { .index = X2APIC_MSR(APIC_LDR),                .always = false }, > +       { .index = X2APIC_MSR(APIC_DFR),                .always = false }, > +       { .index = X2APIC_MSR(APIC_SPIV),               .always = false }, > +       { .index = X2APIC_MSR(APIC_ISR),                .always = false }, > +       { .index = X2APIC_MSR(APIC_TMR),                .always = false }, > +       { .index = X2APIC_MSR(APIC_IRR),                .always = false }, > +       { .index = X2APIC_MSR(APIC_ESR),                .always = false }, > +       { .index = X2APIC_MSR(APIC_ICR),                .always = false }, > +       { .index = X2APIC_MSR(APIC_ICR2),               .always = false }, > +       { .index = X2APIC_MSR(APIC_LVTT),               .always = false }, > +       { .index = X2APIC_MSR(APIC_LVTTHMR),            .always = false }, > +       { .index = X2APIC_MSR(APIC_LVTPC),              .always = false }, > +       { .index = X2APIC_MSR(APIC_LVT0),               .always = false }, > +       { .index = X2APIC_MSR(APIC_LVT1),               .always = false }, > +       { .index = X2APIC_MSR(APIC_LVTERR),             .always = false }, > +       { .index = X2APIC_MSR(APIC_TMICT),              .always = false }, > +       { .index = X2APIC_MSR(APIC_TMCCT),              .always = false }, > +       { .index = X2APIC_MSR(APIC_TDCR),               .always = false }, >         { .index = MSR_INVALID,                         .always = false }, Ouch. Reviewed-by: Maxim Levitsky Best regards, Maxim Levitsky >  }; >