Re: [PATCH v4] PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)

[Siddharth Vadapalli <s-vadapalli@ti.com>]

On Fri, Jun 28, 2024 at 08:14:41AM +0200, Jan Kiszka wrote:
> From: Kishon Vijay Abraham I <kishon@ti.com>
> 
> Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0
> (SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an
> inbound PCIe TLP spans more than two internal AXI 128-byte bursts,
> the bus may corrupt the packet payload and the corrupt data may
> cause associated applications or the processor to hang.
> 
> The workaround for Errata #i2037 is to limit the maximum read
> request size and maximum payload size to 128 bytes. Add workaround
> for Errata #i2037 here. The errata and workaround is applicable
> only to AM65x SR 1.0 and later versions of the silicon will have
> this fixed.
> 
> [1] -> http://www.ti.com/lit/er/sprz452d/sprz452d.pdf

nitpick: The above link redirects to:
https://www.ti.com/lit/er/sprz452i/sprz452i.pdf
So it is still valid, but it might be a good idea to use the updated
link and also update the commit message accordingly:
Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0
(SPRZ452I_JULY_2018_REVISED_MAY_2023 [1]) ...
The updated link also uses "https" instead of "http" which is better.

> 
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Achal Verma <a-verma1@ti.com>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>

Thank you for updating the patch.

Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>

[...]

Regards,
Siddharth.