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Sun, 19 Jan 2025 10:38:28 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50JAcRmN024855 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 19 Jan 2025 10:38:27 GMT Received: from [10.216.35.245] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 19 Jan 2025 02:38:23 -0800 Message-ID: <71635b71-71e4-4c17-add1-bf41ce770632@quicinc.com> Date: Sun, 19 Jan 2025 16:08:20 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: Add cpu scaling clock node To: Dmitry Baryshkov CC: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ajit Pandey , Imran Shaik , "Jagadeesh Kona" , , , References: <20241108-qcs615-mm-dt-nodes-v1-0-b2669cac0624@quicinc.com> <20241108-qcs615-mm-dt-nodes-v1-2-b2669cac0624@quicinc.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: hu3b5rSfPbKc1KZAiuHNekXvn3suSMtK X-Proofpoint-GUID: hu3b5rSfPbKc1KZAiuHNekXvn3suSMtK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-18_10,2025-01-16_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxlogscore=999 priorityscore=1501 bulkscore=0 mlxscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 suspectscore=0 malwarescore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501190086 On 11/9/2024 5:30 AM, Dmitry Baryshkov wrote: > On Fri, Nov 08, 2024 at 11:54:05AM +0530, Taniya Das wrote: >> Add cpufreq-hw node to support cpu frequency scaling. > > CPU, not cpu. > Also the prefix is incorrect for both patches. > Will update to CPU. >> >> Signed-off-by: Taniya Das >> --- >> arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++ >> 1 file changed, 29 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> index 8c98ac77dc5c665ef296e65ac76c1b59be485abb..2c61da790e78b131e454991c968ece40dd5ca56d 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> @@ -33,6 +33,8 @@ cpu0: cpu@0 { >> power-domains = <&cpu_pd0>; >> power-domain-names = "psci"; >> next-level-cache = <&l2_0>; >> + clocks = <&cpufreq_hw 0>; >> + qcom,freq-domain = <&cpufreq_hw 0>; >> #cooling-cells = <2>; >> >> l2_0: l2-cache { >> @@ -51,6 +53,8 @@ cpu1: cpu@100 { >> power-domains = <&cpu_pd1>; >> power-domain-names = "psci"; >> next-level-cache = <&l2_100>; >> + clocks = <&cpufreq_hw 0>; >> + qcom,freq-domain = <&cpufreq_hw 0>; >> >> l2_100: l2-cache { >> compatible = "cache"; >> @@ -68,6 +72,8 @@ cpu2: cpu@200 { >> power-domains = <&cpu_pd2>; >> power-domain-names = "psci"; >> next-level-cache = <&l2_200>; >> + clocks = <&cpufreq_hw 0>; >> + qcom,freq-domain = <&cpufreq_hw 0>; >> >> l2_200: l2-cache { >> compatible = "cache"; >> @@ -85,6 +91,8 @@ cpu3: cpu@300 { >> power-domains = <&cpu_pd3>; >> power-domain-names = "psci"; >> next-level-cache = <&l2_300>; >> + clocks = <&cpufreq_hw 0>; >> + qcom,freq-domain = <&cpufreq_hw 0>; >> >> l2_300: l2-cache { >> compatible = "cache"; >> @@ -102,6 +110,8 @@ cpu4: cpu@400 { >> power-domains = <&cpu_pd4>; >> power-domain-names = "psci"; >> next-level-cache = <&l2_400>; >> + clocks = <&cpufreq_hw 0>; >> + qcom,freq-domain = <&cpufreq_hw 0>; >> >> l2_400: l2-cache { >> compatible = "cache"; >> @@ -119,6 +129,8 @@ cpu5: cpu@500 { >> power-domains = <&cpu_pd5>; >> power-domain-names = "psci"; >> next-level-cache = <&l2_500>; >> + clocks = <&cpufreq_hw 0>; >> + qcom,freq-domain = <&cpufreq_hw 0>; >> >> l2_500: l2-cache { >> compatible = "cache"; >> @@ -136,6 +148,8 @@ cpu6: cpu@600 { >> power-domains = <&cpu_pd6>; >> power-domain-names = "psci"; >> next-level-cache = <&l2_600>; >> + clocks = <&cpufreq_hw 1>; >> + qcom,freq-domain = <&cpufreq_hw 1>; >> #cooling-cells = <2>; >> >> l2_600: l2-cache { >> @@ -154,6 +168,8 @@ cpu7: cpu@700 { >> power-domains = <&cpu_pd7>; >> power-domain-names = "psci"; >> next-level-cache = <&l2_700>; >> + clocks = <&cpufreq_hw 1>; >> + qcom,freq-domain = <&cpufreq_hw 1>; >> >> l2_700: l2-cache { >> compatible = "cache"; >> @@ -729,6 +745,19 @@ rpmhpd_opp_turbo_l1: opp-9 { >> }; >> }; >> >> + cpufreq_hw: cpufreq@18323000 { >> + compatible = "qcom,cpufreq-hw"; > > This doesn't follow the bindings, does it? I will add and re-use the closest target compatible. > >> + reg = <0 0x18323000 0 0x1400>, >> + <0 0x18325800 0 0x1400>; >> + reg-names = "freq-domain0", "freq-domain1"; >> + >> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; >> + clock-names = "xo", "alternate"; > > Are the DCVSH interrupts? > This target does not have DCVSH interrupts directly connected to the CPUFREQ-HW. >> + >> + #freq-domain-cells = <1>; >> + #clock-cells = <1>; >> + }; >> + >> arch_timer: timer { >> compatible = "arm,armv8-timer"; >> interrupts = , >> >> -- >> 2.45.2 >> > -- Thanks & Regards, Taniya Das.