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Decode the count, GMC IDs and flags into GspStaticInfo and expose host-driven engines in firmware FIFO order, retaining repeated IDs. Reject counts and indexed entries beyond the driver's 64-entry table capacity rather than silently accepting a prefix. An omitted count remains zero. Cc: Alexandre Courbot Signed-off-by: Alok Kumar Co-developed-by: Zhi Wang Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/gsp/commands.rs | 2 +- drivers/gpu/nova-core/gsp/fw/commands.rs | 80 ++++++++++++++++++++++++ 2 files changed, 81 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/gsp/commands.rs index 9473004a0921..436ea52689b9 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -126,7 +126,7 @@ pub(crate) fn gsp_init( /// # Errors /// /// - `EINVAL` if the payload is not a whole number of NVKV words, or if the stream is malformed -/// or omits a required key. +/// or omits a required key, or the FIFO engine count exceeds the supported table capacity. /// - `ENOMEM` if the words or the decoded regions cannot be allocated. fn decode_gsp_init_reply(payload_0: &[u8], payload_1: &[u8]) -> Result { const WORD_SIZE: usize = size_of::(); diff --git a/drivers/gpu/nova-core/gsp/fw/commands.rs b/drivers/gpu/nova-core/gsp/fw/commands.rs index d0715dca1be2..17ae4224e214 100644 --- a/drivers/gpu/nova-core/gsp/fw/commands.rs +++ b/drivers/gpu/nova-core/gsp/fw/commands.rs @@ -29,6 +29,7 @@ DecoderValue, Encodable, Encoder, + Indexed, Key, KeyId, Required, // @@ -317,6 +318,52 @@ pub(crate) fn new( // Decode: +const MAX_FIFO_ENGINES: usize = 64; + +/// Bit mask for `NVGMC_SC_ENGINE_FLAGS_IS_HOST_DRIVEN`. +const ENGINE_FLAGS_IS_HOST_DRIVEN: u32 = 1 << 0; + +/// Host-driven GMC engine IDs in hardware FIFO order, including any repeated IDs. +/// +/// # Invariants +/// +/// `count` is at most [`MAX_FIFO_ENGINES`]. The first `count` slots are the retained engine IDs. +#[derive(Copy, Clone)] +pub(crate) struct FifoEngineList { + gmc_ids: [u32; MAX_FIFO_ENGINES], + count: usize, +} + +impl FifoEngineList { + #[expect(dead_code)] + pub(crate) fn gmc_ids(&self) -> &[u32] { + // PANIC: The type invariant bounds `count` by the array capacity. + &self.gmc_ids[..self.count] + } +} + +/// A FIFO engine count that fits the supported tables. +/// +/// # Invariants +/// +/// The count is at most [`MAX_FIFO_ENGINES`]. +#[derive(Default)] +struct FifoEngineCount(usize); + +impl TryFrom> for FifoEngineCount { + type Error = Error; + + fn try_from(value: DecoderValue<'_>) -> Result { + let count = crate::num::u32_as_usize(u32::try_from(value)?); + if count > MAX_FIFO_ENGINES { + Err(EINVAL) + } else { + // INVARIANT: The count was checked against the table capacity above. + Ok(Self(count)) + } + } +} + // Should decode with UnknownKeyPolicy::Ignore. nvkv_decode! { /// Schema for the `GSP_INIT` response. @@ -326,6 +373,9 @@ pub(crate) struct GspInitResponseSchema => GspStaticInfo { fb_regions: Accumulated, bar1_pde_base: Required, vmmu_segment_size: Key, + fifo_engine_count: Key, + fifo_engine_gmc_ids: Indexed, + fifo_engine_flags: Indexed, } } @@ -334,6 +384,9 @@ impl GspInitResponseSchema { const GPU_NAME_STRING_KEY: KeyId = 0x2000; const BAR1_PDE_BASE_KEY: KeyId = 0x1020; const VMMU_SEGMENT_SIZE_KEY: KeyId = 0x1050; + const FIFO_ENGINE_COUNT_KEY: KeyId = 0x0500; + const FIFO_ENGINE_GMC_ID_KEY: KeyId = 0x0501; + const FIFO_ENGINE_FLAGS_KEY: KeyId = 0x0502; } /// The static GPU configuration, as decoded from the `GSP_INIT` reply. @@ -343,6 +396,9 @@ pub(crate) struct GspStaticInfo { bar1_pde_base: u64, #[cfg_attr(not(CONFIG_KUNIT = "y"), expect(dead_code))] vmmu_segment_size: u64, + fifo_engine_count: FifoEngineCount, + fifo_engine_gmc_ids: [u32; MAX_FIFO_ENGINES], + fifo_engine_flags: [u32; MAX_FIFO_ENGINES], } /// Error type for [`GspStaticInfo::gpu_name`]. @@ -407,6 +463,30 @@ pub(crate) fn total_fb_end(&self) -> Option { .checked_add(1) } + /// Returns the host-driven engines in their firmware FIFO order. + #[expect(dead_code)] + pub(crate) fn fifo_engine_list(&self) -> FifoEngineList { + // INVARIANT: The list starts empty and appends at most one ID per supported input slot. + let mut fifo_engine_list = FifoEngineList { + gmc_ids: [0; MAX_FIFO_ENGINES], + count: 0, + }; + for (&gmc_id, &flags) in self + .fifo_engine_gmc_ids + .iter() + .zip(&self.fifo_engine_flags) + .take(self.fifo_engine_count.0) + { + if flags & ENGINE_FLAGS_IS_HOST_DRIVEN != 0 { + // PANIC: At most one slot is filled per input, and the input has at most + // MAX_FIFO_ENGINES entries, so the next retained ID always fits. + fifo_engine_list.gmc_ids[fifo_engine_list.count] = gmc_id; + fifo_engine_list.count += 1; + } + } + fifo_engine_list + } + /// Returns the BAR1 page directory entry base address. pub(crate) fn bar1_pde_base(&self) -> u64 { self.bar1_pde_base