From: <Claudiu.Beznea@microchip.com>
To: <Nicolas.Ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>
Cc: <Sandeep.Sheriker@microchip.com>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>
Subject: Re: [PATCH] ARM: dts: at91: sam9x60: fix the ddr clock for sam9x60
Date: Thu, 12 Jan 2023 12:23:15 +0000 [thread overview]
Message-ID: <71af3b87-2bc5-b518-85c7-b4510fe56175@microchip.com> (raw)
In-Reply-To: <20221208115241.36312-1-claudiu.beznea@microchip.com>
On 08.12.2022 13:52, Claudiu Beznea wrote:
> The 2nd DDR clock for sam9x60 DDR controller is peripheral clock with
> id 49.
>
> Fixes: 1e5f532c2737 ("ARM: dts: at91: sam9x60: add device tree for soc and board")
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Applied to at91-fixes, thanks!
> ---
> arch/arm/boot/dts/sam9x60.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
> index 8f5477e307dd..37a5d96aaf64 100644
> --- a/arch/arm/boot/dts/sam9x60.dtsi
> +++ b/arch/arm/boot/dts/sam9x60.dtsi
> @@ -564,7 +564,7 @@ pmecc: ecc-engine@ffffe000 {
> mpddrc: mpddrc@ffffe800 {
> compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
> reg = <0xffffe800 0x200>;
> - clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
> + clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>;
> clock-names = "ddrck", "mpddr";
> };
>
prev parent reply other threads:[~2023-01-12 12:23 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-08 11:52 Claudiu Beznea
2023-01-12 12:23 ` Claudiu.Beznea [this message]
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