From: "quanyang.wang" <quanyang.wang@windriver.com>
To: Michal Simek <michal.simek@xilinx.com>,
linux-kernel@vger.kernel.org, monstr@monstr.eu, git@xilinx.com,
Viresh Kumar <viresh.kumar@linaro.org>
Cc: Krzysztof Kozlowski <krzk@kernel.org>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 25/31] arm64: zynqmp: Wire qspi on multiple boards
Date: Thu, 10 Jun 2021 12:08:11 +0800 [thread overview]
Message-ID: <71b6423c-ab14-424f-0018-fafece13150a@windriver.com> (raw)
In-Reply-To: <80671218c97ad2188df476cf1b49bcf6f64785df.1623239033.git.michal.simek@xilinx.com>
Hi Michal,
On 6/9/21 7:45 PM, Michal Simek wrote:
> Couple of boards have qspi on the board that's why enable controller and
> describe them.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
> .../arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 16 +++++++++++++++-
> .../arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 16 +++++++++++++++-
> .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 14 ++++++++++++++
> .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 14 ++++++++++++++
> .../arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 15 +++++++++++++++
> .../arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 14 ++++++++++++++
> .../arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 4 ++++
> .../arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 15 +++++++++++++++
> .../arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 15 +++++++++++++++
> 9 files changed, 121 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> index 2e05fa416955..f1598527e5ec 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> @@ -2,7 +2,7 @@
> /*
> * dts file for Xilinx ZynqMP ZC1232
> *
> - * (C) Copyright 2017 - 2019, Xilinx, Inc.
> + * (C) Copyright 2017 - 2021, Xilinx, Inc.
> *
> * Michal Simek <michal.simek@xilinx.com>
> */
> @@ -19,6 +19,7 @@ / {
> aliases {
> serial0 = &uart0;
> serial1 = &dcc;
> + spi0 = &qspi;
> };
>
> chosen {
> @@ -36,6 +37,19 @@ &dcc {
> status = "okay";
> };
>
> +&qspi {
> + status = "okay";
> + flash@0 {
> + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x0>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <4>;
> + spi-max-frequency = <108000000>; /* Based on DC1 spec */
> + };
> +};
> +
> &sata {
> status = "okay";
> /* SATA OOB timing settings */
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> index 3d0aaa02f184..04efa1683eaa 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> @@ -2,7 +2,7 @@
> /*
> * dts file for Xilinx ZynqMP ZC1254
> *
> - * (C) Copyright 2015 - 2019, Xilinx, Inc.
> + * (C) Copyright 2015 - 2021, Xilinx, Inc.
> *
> * Michal Simek <michal.simek@xilinx.com>
> * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
> @@ -20,6 +20,7 @@ / {
> aliases {
> serial0 = &uart0;
> serial1 = &dcc;
> + spi0 = &qspi;
> };
>
> chosen {
> @@ -37,6 +38,19 @@ &dcc {
> status = "okay";
> };
>
> +&qspi {
> + status = "okay";
> + flash@0 {
> + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x0>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
> + spi-max-frequency = <108000000>; /* Based on DC1 spec */
> + };
> +};
> +
> &uart0 {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
> index cd406947ec34..9f176307b62a 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
> @@ -26,6 +26,7 @@ aliases {
> mmc1 = &sdhci1;
> rtc0 = &rtc;
> serial0 = &uart0;
> + spi0 = &qspi;
> };
>
> chosen {
> @@ -339,6 +340,19 @@ conf {
> };
> };
>
> +&qspi {
> + status = "okay";
> + flash@0 {
> + compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x0>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <4>;
> + spi-max-frequency = <108000000>; /* Based on DC1 spec */
> + };
> +};
> +
> &rtc {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
> index 8046f0df0f35..05a2b79738af 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
> @@ -26,6 +26,7 @@ aliases {
> rtc0 = &rtc;
> serial0 = &uart0;
> serial1 = &uart1;
> + spi0 = &qspi;
> };
>
> chosen {
> @@ -161,6 +162,19 @@ &i2c1 {
> status = "okay";
> };
>
> +&qspi {
> + status = "okay";
> + flash@0 {
> + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x0>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <4>; /* also DUAL configuration possible */
> + spi-max-frequency = <108000000>; /* Based on DC1 spec */
> + };
> +};
> +
> &rtc {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> index 3cbc51b4587d..becfc23a5610 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> @@ -30,6 +30,7 @@ aliases {
> serial0 = &uart0;
> serial1 = &uart1;
> serial2 = &dcc;
> + spi0 = &qspi;
> };
>
> chosen {
> @@ -934,6 +935,20 @@ &psgtr {
> clock-names = "ref0", "ref1", "ref2", "ref3";
> };
>
> +&qspi {
> + status = "okay";
> + is-dual = <1>;
> + flash@0 {
> + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
Maybe here should be "64MB" not "32MB".
There are 2 mt25qu512a flashes at zcu102 board, and each of them is
64MB. Since "is-dual" mode is not enabled, so we can only observe 64MB
size from boot log:
spi-nor spi0.0: found mt25qu512a, expected m25p80
spi-nor spi0.0: mt25qu512a (65536 Kbytes)
And I only verify the flash size in zcu102 board and not sure if the
flash size comments are correct for other boards in this patch.
Thanks,
Quanyang
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x0>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
> + spi-max-frequency = <108000000>; /* Based on DC1 spec */
> + };
> +};
> +
> &rtc {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
> index 4c328569c3ac..84c4a9003e2e 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
> @@ -28,6 +28,7 @@ aliases {
> serial0 = &uart0;
> serial1 = &uart1;
> serial2 = &dcc;
> + spi0 = &qspi;
> };
>
> chosen {
> @@ -427,6 +428,19 @@ &psgtr {
> clock-names = "ref1", "ref2", "ref3";
> };
>
> +&qspi {
> + status = "okay";
> + flash@0 {
> + compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x0>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <4>;
> + spi-max-frequency = <108000000>; /* Based on DC1 spec */
> + };
> +};
> +
> &sata {
> status = "okay";
> /* SATA OOB timing settings */
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
> index 99d172867f6a..fb8d76b5c27f 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
> @@ -28,6 +28,7 @@ aliases {
> serial0 = &uart0;
> serial1 = &uart1;
> serial2 = &dcc;
> + spi0 = &qspi;
> };
>
> chosen {
> @@ -435,6 +436,9 @@ flash@0 {
> #address-cells = <1>;
> #size-cells = <1>;
> reg = <0x0>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <4>;
> + spi-max-frequency = <108000000>; /* Based on DC1 spec */
> };
> };
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> index 464a76a13c24..d2219373580a 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> @@ -30,6 +30,7 @@ aliases {
> serial0 = &uart0;
> serial1 = &uart1;
> serial2 = &dcc;
> + spi0 = &qspi;
> };
>
> chosen {
> @@ -928,6 +929,20 @@ &psgtr {
> clock-names = "ref1", "ref2", "ref3";
> };
>
> +&qspi {
> + status = "okay";
> + is-dual = <1>;
> + flash@0 {
> + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x0>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
> + spi-max-frequency = <108000000>; /* Based on DC1 spec */
> + };
> +};
> +
> &rtc {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
> index c9d41d16c3f0..4dc315ee91b7 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
> @@ -29,6 +29,7 @@ aliases {
> rtc0 = &rtc;
> serial0 = &uart0;
> serial1 = &dcc;
> + spi0 = &qspi;
> };
>
> chosen {
> @@ -772,6 +773,20 @@ &psgtr {
> clock-names = "ref1", "ref2", "ref3";
> };
>
> +&qspi {
> + status = "okay";
> + is-dual = <1>;
> + flash@0 {
> + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x0>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
> + spi-max-frequency = <108000000>; /* Based on DC1 spec */
> + };
> +};
> +
> &rtc {
> status = "okay";
> };
>
next prev parent reply other threads:[~2021-06-10 4:10 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-09 11:44 [PATCH 00/31] arm64: zynqmp: Extend board description Michal Simek
2021-06-09 11:44 ` [PATCH 01/31] arm64: zynqmp: Disable CCI by default Michal Simek
2021-06-09 11:44 ` [PATCH 02/31] arm64: zynqmp: Do not duplicate flash partition label property Michal Simek
2021-06-09 11:44 ` [PATCH 03/31] arm64: zynqmp: Enable fpd_dma for zcu104 platforms Michal Simek
2021-06-09 11:44 ` [PATCH 04/31] arm64: zynqmp: Fix irps5401 device nodes Michal Simek
2021-06-09 11:44 ` [PATCH 05/31] arm64: zynqmp: Add pinctrl description for all boards Michal Simek
2021-06-09 11:44 ` [PATCH 06/31] arm64: zynqmp: Correct zcu111 psgtr description Michal Simek
2021-06-09 11:44 ` [PATCH 07/31] arm64: zynqmp: Wire psgtr for zc1751-xm015 Michal Simek
2021-06-09 11:44 ` [PATCH 08/31] arm64: zynqmp: Correct psgtr description for zcu100-revC Michal Simek
2021-06-09 11:44 ` [PATCH 09/31] arm64: zynqmp: Add phy description for usb3.0 Michal Simek
2021-06-09 11:44 ` [PATCH 10/31] arm64: zynqmp: Disable WP on zcu111 Michal Simek
2021-06-09 11:44 ` [PATCH 11/31] arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi Michal Simek
2021-06-09 11:44 ` [PATCH 12/31] arm64: zynqmp: Add missing mio-bank properties to dc1 and dc5 Michal Simek
2021-06-09 11:44 ` [PATCH 13/31] arm64: zynqmp: Wire DP and DPDMA for dc1/dc4 Michal Simek
2021-06-09 11:44 ` [PATCH 14/31] arm64: zynqmp: Enable nand driver for dc2 and dc3 Michal Simek
2021-06-09 11:44 ` [PATCH 15/31] arm64: zynqmp: Remove additional newline Michal Simek
2021-06-09 11:44 ` [PATCH 16/31] arm64: zynqmp: Move clock node to zynqmp-clk-ccf.dtsi Michal Simek
2021-06-09 11:44 ` [PATCH 17/31] arm64: zynqmp: Add nvmem alises for eeproms Michal Simek
2021-06-09 11:44 ` [PATCH 18/31] arm64: zynqmp: List reset property for ethernet phy Michal Simek
2021-06-09 11:44 ` [PATCH 19/31] arm64: zynqmp: Add reset-on-timeout to all boards and modify default timeout value Michal Simek
2021-06-09 11:44 ` [PATCH 20/31] arm64: zynqmp: Remove can aliases from zc1751 Michal Simek
2021-06-09 11:44 ` [PATCH 21/31] arm64: zynqmp: Move DP nodes to the end of file on zcu106 Michal Simek
2021-06-10 1:35 ` Laurent Pinchart
2021-06-09 11:44 ` [PATCH 22/31] arm64: zynqmp: Add note about UHS mode on some boards Michal Simek
2021-06-09 11:44 ` [PATCH 23/31] arm64: zynqmp: Update rtc calibration value Michal Simek
2021-06-09 11:45 ` [PATCH 24/31] arm64: zynqmp: Remove information about dma clock on zcu106 Michal Simek
2021-06-09 11:45 ` [PATCH 25/31] arm64: zynqmp: Wire qspi on multiple boards Michal Simek
2021-06-10 4:08 ` quanyang.wang [this message]
[not found] ` <d8d3f8e9-d59d-be12-05dd-5fa9b64cfcbe@xilinx.com>
2021-06-16 11:15 ` quanyang.wang
2021-06-09 11:45 ` [PATCH 26/31] arm64: zynqmp: Move rtc to different location on zcu104-revA Michal Simek
2021-06-09 11:45 ` [PATCH 27/31] arm64: zynqmp: Add reset description for sata Michal Simek
2021-06-09 11:45 ` [PATCH 28/31] arm64: zynqmp: Sync psgtr node location with zcu104-revA Michal Simek
2021-06-09 11:45 ` [PATCH 29/31] arm64: zynqmp: Remove description for 8T49N287 and si5382 chips Michal Simek
2021-06-09 11:45 ` [PATCH 30/31] arm64: zynqmp: Add support for zcu102-rev1.1 board Michal Simek
2021-06-09 11:45 ` [PATCH 31/31] arm64: zynqmp: Add support for Xilinx Kria SOM board Michal Simek
2021-06-09 12:04 ` Geert Uytterhoeven
2021-06-09 12:19 ` Michal Simek
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