Re: [PATCH 2/3] clk: sprd: Add dt-bindings include file for UMS9620

[Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]

On 29/12/2023 09:51, Chunyan Zhang wrote:
> This file defines all UMS9620 clock indexes. It should be included in
> the DTS file(s) in which there're devices using these clocks.
> 

Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching.

A nit, subject: drop second/last, redundant "bindings". The
"dt-bindings" prefix is already stating that these are bindings.


> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
> ---
>  include/dt-bindings/clock/sprd,ums9620-clk.h | 515 +++++++++++++++++++

This is part of previous patch.


>  1 file changed, 515 insertions(+)
>  create mode 100644 include/dt-bindings/clock/sprd,ums9620-clk.h
> 
> diff --git a/include/dt-bindings/clock/sprd,ums9620-clk.h b/include/dt-bindings/clock/sprd,ums9620-clk.h
> new file mode 100644
> index 000000000000..ed566e1208d7
> --- /dev/null
> +++ b/include/dt-bindings/clock/sprd,ums9620-clk.h
> @@ -0,0 +1,515 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> +/*
> + * Unisoc UMS9620 platform clocks
> + *
> + * Copyright (C) 2020-2023, Unisoc Inc.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_UMS9620_H_
> +#define _DT_BINDINGS_CLK_UMS9620_H_
> +
> +#define CLK_26M_AUD		0
> +#define CLK_13M			1
> +#define CLK_6M5			2
> +#define CLK_4M3			3
> +#define CLK_4M			4
> +#define CLK_2M			5
> +#define CLK_1M			6
> +#define CLK_250K		7
> +#define CLK_16K			8
> +#define CLK_RCO_100M_25M	9
> +#define CLK_RCO_100m_20M	10
> +#define CLK_RCO_100m_4M		11
> +#define CLK_RCO_100m_2M		12
> +#define CLK_RCO_60m_20M		13
> +#define CLK_RCO_60m_4M		14
> +#define CLK_RCO_60m_2M		15
> +#define CLK_PHYR8PLL_GATE	16
> +#define CLK_PSR8PLL_GATE	17
> +#define CLK_CPLL_GATE		18
> +#define CLK_V4NRPLL_GATE	19
> +#define CLK_TGPLL_GATE		20
> +#define CLK_MPLLL_GATE		21
> +#define CLK_MPLLM_GATE		22
> +#define CLK_MPLLB_GATE		23
> +#define CLK_MPLLS_GATE		24
> +#define CLK_DPLL0_GATE		25
> +#define CLK_DPLL1_GATE		26
> +#define CLK_DPLL2_GATE		27
> +#define CLK_GPLL_GATE		28
> +#define CLK_AIPLL_GATE		29
> +#define CLK_VDSPPLL_GATE	30
> +#define CLK_AUDPLL_GATE		31
> +#define CLK_PIXELPLL_GATE	32
> +#define CLK_PMU_GATE_NUM	(CLK_PIXELPLL_GATE + 1)

Drop this and all other numbers. Not a binding and you cannot change it,
if you ever want to add missing clock.


Best regards,
Krzysztof