From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out30-130.freemail.mail.aliyun.com (out30-130.freemail.mail.aliyun.com [115.124.30.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB40B2ED872 for ; Sat, 7 Mar 2026 02:14:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772849682; cv=none; b=m+woA6lqiiTNdceqxQX0k4diMqfOMFC2NKKpSq/4OeDhcQyL1/hv5nT3WsOUFqepzW2IsOIVvI3ds3QuJQtxKjiOBR5Ogh1zUsy0Kg97YiQ4+/utIXz4L2IsBBgMm05a+U74l44gca6DkmrQno2rBbH7Ju9RcLQIBXt8c6IlLTE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772849682; c=relaxed/simple; bh=WuFsp8xfoTbgMY7RmJ/LcWlTH7HQORtUZjCkVZxBRxw=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=efTESc1nAwzGmQX6fO0Q1xKL99+bPEBkQ2oaMALea7FbucpoaMomE5kiBd5W7VNtISyewg5jS4fwVKEZ+abiDRqo4+i+9mjn6XW3BtIFlFDW+cCLEU4koox+S2Z5aXVT3I1n/wInpE45jIgfA+8RDcW0Zqyx94/d+LbbJjf4vCM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=rp8HlAhR; arc=none smtp.client-ip=115.124.30.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="rp8HlAhR" DKIM-Signature:v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1772849677; h=Message-ID:Date:MIME-Version:Subject:To:From:Content-Type; bh=TUiYVvq51PhsvRNPGgaHEtOWm+s6zhtlXs4s+mHmblo=; b=rp8HlAhR6DF0FUZYDtjyvMFmNov8mNXbXHLDIzxu8kIKvqW6P4VhgXeGBVf4vdpF6W46/JSd3AJ1lFaQo9+wqtLgHClTxoemsdqT7VLmLuYPmmrDoO6ln4cCaS0VVXOdEVdR/5647oIOpKyI6U31+z/LFZRozERIirvpFXSSCPA= Received: from 30.42.98.36(mailfrom:baolin.wang@linux.alibaba.com fp:SMTPD_---0X-Ob2yS_1772849674 cluster:ay36) by smtp.aliyun-inc.com; Sat, 07 Mar 2026 10:14:35 +0800 Message-ID: <721abb6a-93a0-4db3-9e69-ef23b253e4f5@linux.alibaba.com> Date: Sat, 7 Mar 2026 10:14:34 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 4/5] arm64: mm: implement the architecture-specific clear_flush_young_ptes() To: Barry Song <21cnbao@gmail.com> Cc: akpm@linux-foundation.org, david@kernel.org, catalin.marinas@arm.com, will@kernel.org, lorenzo.stoakes@oracle.com, ryan.roberts@arm.com, Liam.Howlett@oracle.com, vbabka@suse.cz, rppt@kernel.org, surenb@google.com, mhocko@suse.com, riel@surriel.com, harry.yoo@oracle.com, jannh@google.com, willy@infradead.org, dev.jain@arm.com, linux-mm@kvack.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: From: Baolin Wang In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 3/7/26 5:20 AM, Barry Song wrote: > On Mon, Feb 9, 2026 at 10:07 PM Baolin Wang > wrote: >> >> Implement the Arm64 architecture-specific clear_flush_young_ptes() to enable >> batched checking of young flags and TLB flushing, improving performance during >> large folio reclamation. >> >> Performance testing: >> Allocate 10G clean file-backed folios by mmap() in a memory cgroup, and try to >> reclaim 8G file-backed folios via the memory.reclaim interface. I can observe >> 33% performance improvement on my Arm64 32-core server (and 10%+ improvement >> on my X86 machine). Meanwhile, the hotspot folio_check_references() dropped >> from approximately 35% to around 5%. >> >> W/o patchset: >> real 0m1.518s >> user 0m0.000s >> sys 0m1.518s >> >> W/ patchset: >> real 0m1.018s >> user 0m0.000s >> sys 0m1.018s >> >> Reviewed-by: Ryan Roberts >> Signed-off-by: Baolin Wang > > Reviewed-by: Barry Song Thanks Barry. But this series has been upstreamed, I can not add your reviewed tag. > >> --- >> arch/arm64/include/asm/pgtable.h | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >> >> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h >> index 3dabf5ea17fa..a17eb8a76788 100644 >> --- a/arch/arm64/include/asm/pgtable.h >> +++ b/arch/arm64/include/asm/pgtable.h >> @@ -1838,6 +1838,17 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma, >> return contpte_clear_flush_young_ptes(vma, addr, ptep, 1); >> } >> >> +#define clear_flush_young_ptes clear_flush_young_ptes >> +static inline int clear_flush_young_ptes(struct vm_area_struct *vma, >> + unsigned long addr, pte_t *ptep, >> + unsigned int nr) >> +{ >> + if (likely(nr == 1 && !pte_cont(__ptep_get(ptep)))) >> + return __ptep_clear_flush_young(vma, addr, ptep); >> + >> + return contpte_clear_flush_young_ptes(vma, addr, ptep, nr); >> +} > > A similar question arises here: > > If nr = 4 for 16KB large folios and one of those entries is young, > we end up flushing the TLB for all 4 PTEs. > > If all four entries are young, we win; if only one is young, it seems > we flush 3 redundant pages. but arm64 has TLB coalescing, so > maybe they are just one TLB? We discussed a similar issue in the previous thread [1], and I quote some comments from Ryan: " My concern was the opportunity cost of evicting the entries for all the non-accessed parts of the folio from the TLB. But of course, I'm talking nonsense because the architecture does not allow caching non-accessed entries in the TLB. " [1] https://lore.kernel.org/all/02239ca7-9701-4bfa-af0f-dcf0d05a3e89@linux.alibaba.com/