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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from BL1PR12MB5320.namprd12.prod.outlook.com (2603:10b6:208:314::17) by SJ0PR12MB7008.namprd12.prod.outlook.com (2603:10b6:a03:486::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.546.15; Wed, 21 Oct 2026 18:45:46 +0000 Received: from BL1PR12MB5320.namprd12.prod.outlook.com ([fe80::1876:4a6d:2cf5:b8d1]) by BL1PR12MB5320.namprd12.prod.outlook.com ([fe80::1876:4a6d:2cf5:b8d1%5]) with mapi id 15.21.0546.012; Wed, 21 Oct 2026 18:45:45 +0000 Message-ID: <72328ebb-ec1b-4c6d-ad0e-d422e488a9cb@amd.com> Date: Wed, 21 Oct 2026 13:45:41 -0500 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 00/18] x86,fs/resctrl: Add kernel-mode (e.g., PLZA) support to the resctrl subsystem To: Drew Fustini Cc: Yunhui Cui , tony.luck@intel.com, reinette.chatre@intel.com, bp@alien8.de, ben.horgan@arm.com, corbet@lwn.net, skhan@linuxfoundation.org, rdunlap@infradead.org, x86@kernel.org, Dave.Martin@arm.com, james.morse@arm.com, tglx@kernel.org, mingo@redhat.com, dave.hansen@linux.intel.com, hpa@zytor.com, fenghuay@nvidia.com, kas@kernel.org, rick.p.edgecombe@intel.com, akpm@linux-foundation.org, rppt@kernel.org, dapeng1.mi@linux.intel.com, elver@google.com, enelsonmoore@gmail.com, jlayton@kernel.org, kuba@kernel.org, ebiggers@kernel.org, seanjc@google.com, ewanhai-oc@zhaoxin.com, binbin.wu@linux.intel.com, peterz@infradead.org, ashish.kalra@amd.com, superm1@kernel.org, chang.seok.bae@intel.com, prathyushi.nangia@amd.com, kim.phillips@amd.com, ackerleytng@google.com, elena.reshetova@intel.com, naveen@kernel.org, darwi@linutronix.de, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-coco@lists.linux.dev, kvm@vger.kernel.org, eranian@google.com, peternewman@google.com References: Content-Language: en-US From: Babu Moger In-Reply-To: Content-Type: text/plain; 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It adds a new CSR with a RCID (like CLOSID) and MCID > (like RMID) to use when the cpu switches to the privilege level that the > kernel runs in (supervisor-mode in RISC-V terminology). The srmcfg_assoc > register is defined as: > > Bits Field > -------- -------- > 11:0 RCID > 12 RCID_EN > 15:13 Reserved > 27:16 MCID > 28 MCID_EN > 30:29 Reserved > 31 ASSOC_EN > > It is similar enough to PLZA that I believe that this series could work > for RISC-V. Hopefully Yunhui Cui can comment further. > That's great to hear. Please feel free to share any feedback or suggestions that would make this easier for RISC-V. Thanks, Babu