From: Krzysztof Kozlowski <krzk@kernel.org>
To: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>,
Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Samuel Holland <samuel.holland@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Min Lin <linmin@eswincomputing.com>,
Pritesh Patel <pritesh.patel@einfochips.com>,
Yangyu Chen <cyy@cyyself.name>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Yu Chien Peter Lin <peterlin@andestech.com>,
Charlie Jenkins <charlie@rivosinc.com>,
Kanak Shilledar <kanakshilledar@gmail.com>,
Darshan Prajapati <darshan.prajapati@einfochips.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Heiko Stuebner <heiko@sntech.de>,
Aradhya Bhatia <a-bhatia1@ti.com>,
"rafal@milecki.pl" <rafal@milecki.pl>,
Anup Patel <anup@brainfault.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [External] Re: [PATCH v4 0/7] Basic device tree support for ESWIN EIC7700 RISC-V SoC
Date: Mon, 4 Aug 2025 16:45:10 +0200 [thread overview]
Message-ID: <72354ec9-7dc8-4192-9c25-d37abf33b5f0@kernel.org> (raw)
In-Reply-To: <SA3PR04MB89312063FB96E85ABB6F3D3E8323A@SA3PR04MB8931.namprd04.prod.outlook.com>
On 04/08/2025 15:10, Pinkesh Vaghela wrote:
> Hello Krzysztof,
>
> Sorry to bother you. I pinged because we addressed all the review comments of V3 in V4. But on V4 we have not received any comments since last 6 weeks.
> Could you please let us know what should be the further steps?
Please don't top post.
That is a bit different question than you asked before: "Gentle reminder
to review DT patches.".
Please read SoC subsystem maintainer profile document. For ARM platforms
you would send now pull request or patches to soc. For RISC-V - not sure
some trees are handled by Conor, but rest go directly to soc tree.
I would suggest following standard SoC way, same as for every other new
SoC (but carefully observe the kernel process cycle). You can easily
check archives to see how people also did it...
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-08-04 14:45 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-16 11:23 Pinkesh Vaghela
2025-06-16 11:23 ` [PATCH v4 1/7] dt-bindings: riscv: Add SiFive P550 CPU compatible Pinkesh Vaghela
2025-06-16 11:23 ` [PATCH v4 2/7] riscv: Add Kconfig option for ESWIN platforms Pinkesh Vaghela
2025-06-16 11:23 ` [PATCH v4 3/7] dt-bindings: vendor-prefixes: add eswin Pinkesh Vaghela
2025-08-21 19:11 ` Rob Herring
2025-06-16 11:23 ` [PATCH v4 4/7] dt-bindings: riscv: Add SiFive HiFive Premier P550 board Pinkesh Vaghela
2025-06-16 11:23 ` [PATCH v4 5/7] dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC Pinkesh Vaghela
2025-06-16 11:23 ` [PATCH v4 6/7] riscv: dts: add initial support for EIC7700 SoC Pinkesh Vaghela
2025-06-16 11:23 ` [PATCH v4 7/7] riscv: dts: eswin: add HiFive Premier P550 board device tree Pinkesh Vaghela
2025-08-01 10:34 ` [PATCH v4 0/7] Basic device tree support for ESWIN EIC7700 RISC-V SoC Pinkesh Vaghela
2025-08-02 8:34 ` Krzysztof Kozlowski
2025-08-04 13:10 ` [External] " Pinkesh Vaghela
2025-08-04 14:45 ` Krzysztof Kozlowski [this message]
2025-08-05 14:21 ` Conor Dooley
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