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Tue, 26 Nov 2024 09:51:25 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 21B2440057; Tue, 26 Nov 2024 09:49:44 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 33D08269E1E; Tue, 26 Nov 2024 09:47:19 +0100 (CET) Received: from [10.129.178.23] (10.129.178.23) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Tue, 26 Nov 2024 09:47:18 +0100 Message-ID: <725aafb8-abfa-40c0-967a-62122206f736@foss.st.com> Date: Tue, 26 Nov 2024 09:47:17 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] drm/modes: introduce drm_mode_validate_mode() helper function To: Sean Nyekjaer , Maxime Ripard CC: Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Yannick Fertre , Philippe Cornu , Maxime Coquelin , Alexandre Torgue , , , , , References: <20241125-dsi-relax-v2-0-9113419f4a40@geanix.com> <20241125-dsi-relax-v2-1-9113419f4a40@geanix.com> <20241125-gleaming-anteater-of-perfection-42bd2b@houat> Content-Language: en-US From: Raphael Gallais-Pou In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 On 11/26/24 08:36, Sean Nyekjaer wrote: > Hi Maxime, > > On Mon, Nov 25, 2024 at 05:00:56PM +0100, Maxime Ripard wrote: >> Hi Sean, >> >> On Mon, Nov 25, 2024 at 02:49:26PM +0100, Sean Nyekjaer wrote: >>> Check if the required pixel clock is in within .5% range of the >>> desired pixel clock. >>> This will match the requirement for HDMI where a .5% tolerance is allowed. >>> >>> Signed-off-by: Sean Nyekjaer >>> --- >>> drivers/gpu/drm/drm_modes.c | 34 ++++++++++++++++++++++++++++++++++ >>> include/drm/drm_modes.h | 2 ++ >>> 2 files changed, 36 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c >>> index 6ba167a3346134072d100af0adbbe9b49e970769..4068b904759bf80502efde6e4d977b297f5d5359 100644 >>> --- a/drivers/gpu/drm/drm_modes.c >>> +++ b/drivers/gpu/drm/drm_modes.c >>> @@ -1623,6 +1623,40 @@ bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1, >>> } >>> EXPORT_SYMBOL(drm_mode_equal_no_clocks_no_stereo); >>> >>> +/** >>> + * drm_mode_validate_mode >>> + * @mode: mode to check >>> + * @rounded_rate: output pixel clock >>> + * >>> + * VESA DMT defines a tolerance of 0.5% on the pixel clock, while the >>> + * CVT spec reuses that tolerance in its examples, so it looks to be a >>> + * good default tolerance for the EDID-based modes. Define it to 5 per >>> + * mille to avoid floating point operations. >>> + * >>> + * Returns: >>> + * The mode status >>> + */ >>> +enum drm_mode_status drm_mode_validate_mode(const struct drm_display_mode *mode, >>> + unsigned long long rounded_rate) >>> +{ >>> + enum drm_mode_status status; >>> + unsigned long long rate = mode->clock * 1000; >>> + unsigned long long lowest, highest; >>> + >>> + lowest = rate * (1000 - 5); >>> + do_div(lowest, 1000); >>> + if (rounded_rate < lowest) >>> + return MODE_CLOCK_LOW; >>> + >>> + highest = rate * (1000 + 5); >>> + do_div(highest, 1000); >>> + if (rounded_rate > highest) >>> + return MODE_CLOCK_HIGH; >>> + >>> + return MODE_OK; >>> +} >>> +EXPORT_SYMBOL(drm_mode_validate_mode); Hi Sean, Maxime, >> Thanks a lot for doing that! >> >> I wonder about the naming though (and prototype). I doesn't really >> validates a mode, but rather makes sure that a given rate is a good >> approximation of a pixel clock. So maybe something like >> drm_mode_check_pixel_clock? > Naming is hard :) I will use drm_mode_check_pixel_clock() for V2. > > Would it make sense to have the pixel clock requirement as a input > parameter? For HDMI it is 0.5% and in my case the LVDS panel 10%. > > enum drm_mode_status drm_mode_validate_mode(const struct drm_display_mode *mode, > unsigned long long rounded_rate, unsigned tolerance) > ? IMO adding the tolerance as input parameter is a good idea.  This would useful other than for HDMI pixel clock validation (and LVDS in your case). Best regards, Raphaël > > And maybe a drm_mode_validate_mode_hdmi() with the default tolerance of > .5%? >> We probably need some kunit tests here too. > Good idea, will be my first :) > > /Sean