From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE767BE4F for ; Fri, 2 Aug 2024 01:44:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.189 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722563051; cv=none; b=EJpcxb3a44de30YnuagkKGTpPhfgsvyVSK8DKm2Db7ZqVrxr1LQIjsAnzaLbPo4LW+dehaQ1x7S9AeaYuGl/bum3926sosteoxxN9A4pggtKr4ygFSgd2VNJwjwK5S/SQslsregob8GublJPjjabolbJONM7UWdtv9Ma65rxaho= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722563051; c=relaxed/simple; bh=R30IIuwa6mus94ESdV3N3TVFOozI//ZVq5AxdhdwD3o=; h=Message-ID:Date:MIME-Version:Subject:From:To:CC:References: In-Reply-To:Content-Type; b=ipnrr/IZMKFKC5BsBQc/UV8mPOqslZr0XnokHazXEDaMdLYBvBk40C5+/zoXy7Z+vmLMikty/Qn7B8+xaJpYpH0CpJmvAWkOqCOm/R6M3lWJ/5SoCBXKmXqkhDg0hzSE+8CkqYxepuplJaVblyR4FCgc4mSVHVEJ4T+9adVQ2cw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.189 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.194]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4WZpRM68CGzQngF; Fri, 2 Aug 2024 09:39:43 +0800 (CST) Received: from kwepemi100008.china.huawei.com (unknown [7.221.188.57]) by mail.maildlp.com (Postfix) with ESMTPS id 99A2C140132; Fri, 2 Aug 2024 09:44:04 +0800 (CST) Received: from [10.67.109.254] (10.67.109.254) by kwepemi100008.china.huawei.com (7.221.188.57) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 2 Aug 2024 09:44:03 +0800 Message-ID: <726da253-9827-b5fe-76ef-99b2ec9c42e3@huawei.com> Date: Fri, 2 Aug 2024 09:44:03 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.0 Subject: Re: [PATCH] ARM: smp: Fix missing backtrace IPI statics Content-Language: en-US From: Jinjie Ruan To: "Russell King (Oracle)" CC: , , , , , , References: <20240801094022.1402616-1-ruanjinjie@huawei.com> In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To kwepemi100008.china.huawei.com (7.221.188.57) On 2024/8/2 9:39, Jinjie Ruan wrote: > > > On 2024/8/2 0:36, Russell King (Oracle) wrote: >> On Thu, Aug 01, 2024 at 05:40:22PM +0800, Jinjie Ruan wrote: >>> It is similar to ARM64 commit 916b93f4e865 ("arm64: smp: Fix missing IPI >>> statistics"), commit 56afcd3dbd19 ("ARM: Allow IPIs to be handled as normal >>> interrupts") set CPU_BACKTRACE IPI "IRQ_HIDDEN" flag but not show it in >>> show_ipi_list(), which cause the interrupt kstat_irqs accounting >>> is missing in display. >> >> I don't see why this needs to be included. If this IPI fires, it means >> that the kernel has suffered a lockup and is probably not very useful. >> So the chances of being able to read out from /proc/interrupts a non- >> zero "CPU backtrace interrupts" figure is highly unlikely. > > It is more of a change than a bug. > > If we reset the arm32 code to before commit 56afcd3dbd19 ("ARM: Allow > IPIs to be handled as normal interrupts"), the backtrace IPI statics is > shown ok as below, but after that it is missing: Sorry, there is some mistake here, the original result has no backtrace IPI statics. > > / # cat /proc/interrupts > CPU0 > 24: 6 GIC-0 34 Level timer > 25: 469 GIC-0 29 Level twd > 26: 61 GIC-0 75 Edge virtio0 > 29: 8 GIC-0 44 Level kmi-pl050 > 30: 118 GIC-0 45 Level kmi-pl050 > 31: 0 GIC-0 36 Level rtc-pl031 > 32: 0 GIC-0 41 Level mmci-pl18x (cmd) > 33: 0 GIC-0 42 Level mmci-pl18x (pio) > 34: 0 GIC-0 92 Level arm-pmu > 35: 0 GIC-0 93 Level arm-pmu > 36: 0 GIC-0 94 Level arm-pmu > 37: 0 GIC-0 95 Level arm-pmu > 39: 15 GIC-0 37 Level uart-pl011 > IPI0: 0 CPU wakeup interrupts > IPI1: 0 Timer broadcast interrupts > IPI2: 0 Rescheduling interrupts > IPI3: 0 Function call interrupts > IPI4: 0 CPU stop interrupts > IPI5: 0 IRQ work interrupts > IPI6: 0 completion interrupts > IPI7: 0 CPU backtrace interrupts > > >> >> So, I don't see much point to this change. >>