From: "Chen, Zide" <zide.chen@intel.com>
To: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Xudong Hao <xudong.hao@intel.com>,
Falcon Thomas <thomas.falcon@intel.com>
Subject: Re: [PATCH 5/7] perf/x86/intel/uncore: Support IIO free-running counters on DMR
Date: Tue, 23 Dec 2025 13:54:21 -0800 [thread overview]
Message-ID: <728e95c7-df78-4a6a-80df-7f7e88579440@intel.com> (raw)
In-Reply-To: <c31a79f4-3579-4b67-a859-ec0c69824edc@linux.intel.com>
On 12/22/2025 9:18 PM, Mi, Dapeng wrote:
>
> On 12/13/2025 5:00 AM, Zide Chen wrote:
>> The free-running counters for IIO uncore blocks on Diamond Rapids are
>> similar to Sapphire Rapids IMC freecounters, with the following
>> differences:
>>
>> - The counters are MMIO based.
>> - Only a subset of IP blocks implement free-running counters:
>> HIOP0 (IP Base Addr: 2E7000h)
>> HIOP1 (IP Base Addr: 2EF000h)
>> HIOP3 (IP Base Addr: 2FF000h)
>> HIOP4 (IP Base Addr: 307000h)
>> - IMH2 (Secondary IMH) does not provide free-running counters.
>>
>> Signed-off-by: Zide Chen <zide.chen@intel.com>
>> ---
>> arch/x86/events/intel/uncore_snbep.c | 120 +++++++++++++++++++++++++--
>> 1 file changed, 115 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
>> index 56c6ac86f28e..21cca1b28075 100644
>> --- a/arch/x86/events/intel/uncore_snbep.c
>> +++ b/arch/x86/events/intel/uncore_snbep.c
>> @@ -472,10 +472,14 @@
>> #define SPR_C0_MSR_PMON_BOX_FILTER0 0x200e
>>
>> /* DMR */
>> +#define DMR_IMH1_HIOP_MMIO_BASE 0x1ffff6ae7000
>> +#define DMR_HIOP_MMIO_SIZE 0x8000
>> #define DMR_CXLCM_EVENT_MASK_EXT 0xf
>> #define DMR_HAMVF_EVENT_MASK_EXT 0xffffffff
>> #define DMR_PCIE4_EVENT_MASK_EXT 0xffffff
>>
>> +#define UNCORE_DMR_ITC 0x30
>> +
>> #define DMR_IMC_PMON_FIXED_CTR 0x18
>> #define DMR_IMC_PMON_FIXED_CTL 0x10
>>
>> @@ -6442,7 +6446,11 @@ static int uncore_type_max_boxes(struct intel_uncore_type **types,
>> for (node = rb_first(type->boxes); node; node = rb_next(node)) {
>> unit = rb_entry(node, struct intel_uncore_discovery_unit, node);
>>
>> - if (unit->id > max)
>> + /*
>> + * on DMR IMH2, the unit id starts from 0x8000,
>> + * and we don't need to count it.
>> + */
>> + if ((unit->id > max) && (unit->id < 0x8000))
>> max = unit->id;
>> }
>> return max + 1;
>> @@ -6925,6 +6933,103 @@ int dmr_uncore_units_ignore[] = {
>> UNCORE_IGNORE_END
>> };
>>
>> +static unsigned int dmr_iio_freerunning_box_offsets[] = {
>> + 0x0, 0x8000, 0x18000, 0x20000
>> +};
>> +
>> +static void dmr_uncore_freerunning_init_box(struct intel_uncore_box *box)
>> +{
>> + struct intel_uncore_type *type = box->pmu->type;
>> + u64 mmio_base;
>> +
>> + if (box->pmu->pmu_idx >= type->num_boxes) {
>> + pr_warn("perf uncore: Failed to ioremap for %s.\n", type->name);
>
> The warning message is not quite matched with the error case, please update it.
My mistake. This is only a sanity check to prevent out-of-bounds access
to dmr_iio_freerunning_box_offsets[] and should never be triggered in
practice. I think it is safe to remove the pr_warn().
> Other part looks good to me.
next prev parent reply other threads:[~2025-12-23 21:54 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-12 21:00 [PATCH 0/7] Add Diamond Rapids uncore support Zide Chen
2025-12-12 21:00 ` [PATCH 1/7] perf/x86/intel/uncore: Add dual PCI/MSR discovery support Zide Chen
2025-12-23 3:07 ` Mi, Dapeng
2025-12-12 21:00 ` [PATCH 2/7] perf/x86/intel/uncore: Add IMH PMON support for Diamond Rapids Zide Chen
2025-12-23 3:27 ` Mi, Dapeng
2025-12-12 21:00 ` [PATCH 3/7] perf/x86/intel/uncore: Add CBB " Zide Chen
2025-12-23 3:38 ` Mi, Dapeng
2025-12-12 21:00 ` [PATCH 4/7] perf/x86/intel/uncore: Add freerunning event descriptor helper macro Zide Chen
2025-12-23 3:39 ` Mi, Dapeng
2025-12-12 21:00 ` [PATCH 5/7] perf/x86/intel/uncore: Support IIO free-running counters on DMR Zide Chen
2025-12-23 5:18 ` Mi, Dapeng
2025-12-23 21:54 ` Chen, Zide [this message]
2025-12-12 21:00 ` [PATCH 6/7] perf/x86/intel/uncore: Update DMR uncore constraints preliminarily Zide Chen
2025-12-23 5:52 ` Mi, Dapeng
2025-12-23 21:53 ` Chen, Zide
2025-12-12 21:00 ` [PATCH 7/7] perf pmu: Relax uncore wildcard matching to allow numeric suffix Zide Chen
2025-12-23 5:58 ` Mi, Dapeng
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=728e95c7-df78-4a6a-80df-7f7e88579440@intel.com \
--to=zide.chen@intel.com \
--cc=acme@kernel.org \
--cc=adrian.hunter@intel.com \
--cc=ak@linux.intel.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=dapeng1.mi@linux.intel.com \
--cc=eranian@google.com \
--cc=irogers@google.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=mingo@redhat.com \
--cc=namhyung@kernel.org \
--cc=peterz@infradead.org \
--cc=thomas.falcon@intel.com \
--cc=xudong.hao@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®