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Fri, 23 Oct 2026 02:46:01 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c46a5c4d827sm85500066b.15.2026.10.23.02.45.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 23 Oct 2026 02:46:00 -0700 (PDT) Message-ID: <729312d0-d48b-4c92-ac6c-98ffbb23d7c7@oss.qualcomm.com> Date: Fri, 23 Oct 2026 11:45:58 +0200 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clk: qcom: gcc-ipq6018: add fallback names for the bias PLL parents To: Robert Marko Cc: Julius Bairaktaris , Bjorn Andersson , Stephen Boyd , Abel Vesa , Brian Masney , Jerome Brunet , Vladyslav Andreichykov , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261020065430.1251541-1-julius@bairaktaris.de> <30c21159-3008-463c-9cd2-a07f26668a25@sartura.hr> <9699033c-a9e1-4b11-a55f-b1aa216c700f@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIzMDAzOCBTYWx0ZWRfXzf2rEL/DXXEK fom9WFNN3wmVbmkecUsHcoqt83dDb1kiHmdvNfCPMb+bl/eMabxG4mABqhsp7eqZa/tIa1O8L8i WGYSlSgeGWIKLnrlT+TEMi6AdpoleGs= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIzMDAzOCBTYWx0ZWRfX2wQfFKQWbqIu 6Qg2Vr8yrFPr7UIH7Tj8fb5scHsEbP7EDaW58gVR3UwGc3j1SVzQCTOxBLlY8DX5SV7gRfo2VaL rX/CYaxdGkBU0fUNxeXtn6w19nOe4i6o/T1GmLrEgIKMmyEVqjIupQRr8zb+HMZw2YVEMeZzG/t ZvBw9gmImV8KkY4LVbiKTSE6pTIj+Xssxkk/I/0IYq2tWl6LIGnUL1i9oEAU27gLNIuhlBAtQUH MX3/q/kO5p1HiD78F0CAaT1tkW61B54Uh7s+tMVGDX04w+I+Gv9So8IfN0x/sZU4PArpEsSJK3J Hc2RLQfeuznsKy58HiaHKEzUcDG5fNp0g+VvO6MjmCFgFOlcxIaXcM9YF+wXP92GUXhzqe3hqP7 yC0BCpso9+cBzsP6Kci6OX+HBe0HqSm3ZCiJPKKUIrQWDCiXaRU5KdYOIub9P00vonPNfde4Ghw k7/7jbSOBXAGQrNgTwA== X-Proofpoint-GUID: DWAs0_IWFYaiPCC98UV5Bsd7Y25AoKux X-Authority-Analysis: v=2.4 cv=YIMKWhGx c=1 sm=1 tr=0 ts=6adb2cda cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=pGLkceISAAAA:8 a=Rp3BUHB5SiOdbJK_EPAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-ORIG-GUID: DWAs0_IWFYaiPCC98UV5Bsd7Y25AoKux X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-23_02,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 bulkscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610230038 On 10/23/26 11:41 AM, Robert Marko wrote: > On Wed, Oct 21, 2026 at 10:06 AM Konrad Dybcio > wrote: >> >> On 10/20/26 1:39 PM, Robert Marko wrote: >>> >>> On 20/10/2026 08:54, Julius Bairaktaris wrote: >>>> From: Vladyslav Andreichykov >>>> >>>> bias_pll_cc_clk and bias_pll_nss_noc_clk are outputs of the CMN PLL, >>>> which takes its AHB and SYS clocks from GCC, so the device tree does not >>>> pass them back to GCC. With only .fw_name these parents never resolve, >>>> nss_ppe_clk_src stays an orphan, and setting it to 300 MHz fails with >>>> -EINVAL. The NSS clocks below it, such as gcc_nss_edma_clk, read 0 Hz. >>>> >>>> Add .name fallbacks so they resolve to the clocks the CMN PLL registers, >>>> as gcc-ipq8074 already does. >>>> >>>> Tested-by: Vladyslav Andreichykov >>>> Assisted-by: Claude:claude-opus-5-5 >>>> Signed-off-by: Vladyslav Andreichykov >>>> Signed-off-by: Julius Bairaktaris >>>> --- >>> >>> Hi, >>> >>> This issue does not exist upstream, as CMN PLL is not yet wired due to missing >>> networking, even then the solution is not to add global name matching. >>> >>> The required clock inputs should just be passed to GCC directly which I have >>> just pushed to OpenWrt. >> >> Just read your reply after writing mine, I'm looking forward to seeing >> that patch! > > Hi Konrad, > You mean the wiring for CMN PLL or? Yes the wiring Konrad