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client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by SN1PEPF00036F41.mail.protection.outlook.com (10.167.248.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9769.17 via Frontend Transport; Fri, 10 Apr 2026 06:02:13 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 10 Apr 2026 01:02:12 -0500 Received: from [10.136.36.199] (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Fri, 10 Apr 2026 01:02:10 -0500 Message-ID: <729726b9-c669-41e2-887d-bdf9da703034@amd.com> Date: Fri, 10 Apr 2026 11:32:09 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/4] sched/rt: Split cpupri_vec->cpumask to per NUMA node to reduce contention To: "Chen, Yu C" , Tim Chen , Peter Zijlstra CC: Pan Deng , , , References: <20260320124003.GU3738786@noisy.programming.kicks-ass.net> <63a095f02428700a7ff2623b8ea81e524a406834.camel@linux.intel.com> <20260324120008.GB3738010@noisy.programming.kicks-ass.net> <138c3f9d-309f-41e6-aa72-a3f6bd713bf0@intel.com> <22072ef8-5aec-49ac-9cc4-8a80bec14261@amd.com> <64649c85-29ab-4f70-a0c4-3c83cbdae2fc@intel.com> <20260402105530.GA3738786@noisy.programming.kicks-ass.net> <93d7eb33-c3a5-4498-bc26-57806b73d9e0@amd.com> <3b66e8e8-07e0-4f3e-a3ba-d97133af5162@intel.com> <1c742a1d8ecd8e314d704d46a44e2b8893479e50.camel@linux.intel.com> <2881a07f-ff14-4faa-9da7-3fbe206a463d@amd.com> <14eda829-fc6b-407a-93a3-0794ab521177@intel.com> <2dcbf93d-030d-466c-8b1c-8387513e9eb9@amd.com> <1684620e-7c03-435c-9596-8d12ddba83bd@intel.com> Content-Language: en-US From: K Prateek Nayak In-Reply-To: <1684620e-7c03-435c-9596-8d12ddba83bd@intel.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: E+3T1Kc5t7b1NswK1IkHjpeCyj8Pi8jfeMNDiccqkqn7/Elf9k9JIeRLlYoKVjabrernPKb9Zb8VbQMhPSeWIuLZroDeZP+B1dJnu60gavoVI1R8lRbhlZC7aXP6vVdtNch1IQN/WCcirIfYITvvIAg/sy9hy0d2digmDh8ZXCkA7DE8dkh15iJoyPVzMzDAGzWE3NLMwKKWHlc90xskRaIhK9tWJ7k9dQ2yTu9rEmjVB7CymF1KLQmfyKr/gQrmQfGVtbGK2vZV2HWfV/F+2AsoL8X/2zR5R7eyCg1sx4sJpoijrKlMjZPYVL1FQqPoiLS+bPTwxcfjSm3kjLa3nHsWYWDAwatlzl77wYzliVa0g/8BSXf6b1NbBSSGGvuRoLX+z/89W91LngXZXsbyOPP5xpCWCRzCmGIwiE1jEA1CAXFECrW2VFiXmnPMLler X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2026 06:02:13.8264 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1fbdbcd6-4c38-4bd1-50b7-08de96c6b641 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F41.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6159 Hello Chenyu, Tim, On 4/10/2026 11:21 AM, Chen, Yu C wrote: >>> I think per-LLC mask (or, as Tim suggested, 64CPUs per cacheline) is >>> a good tradeoff between the speedup vs amount of loads required to >>> piece together the full cpumask. Thoughts? > > Yes, making it per LLC should work well enough (for balancing) to > achieve optimal benefit. Let me run some similar tests to yours,plus > hackbench/schbench, to see what the results are. > BTW, on AMD systems, does the TILE domain always match the CCX where > L3 is shared? On Intel the DIE is not always mapped to a domain > where L3 is shared. On AMD platforms that support the extended leaf 0x80000026, CCX is always mapped to L3 and matched the data on 0x8000001D cache property leaf for L3. > >> >> I agree that per-LLC mask is a good compromise between minimizing loads >> and offer good speed ups.  I think we should get the LLC APICID >> mask from 0x4 leaf (L1, L2, L3) instead of inferring from 0x1f leaf (Tile, Die ...etc) >> for Intel.  And the cache leaf I think is 0x8000_001D leaf for AMD. >> Those are parsed in cacheinfo code and we can get it from there. >> > > Yes, let me check how we can leverage the l3 id for that. Ack! I think the cacheinfo is better for all this and is also compatible with older systems that may nit have the extend topology enumeration leaf. AMD only got it two generations ago and until that only cache property leaf was used for marking the LLC (CCX) boundary. -- Thanks and Regards, Prateek