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[82.81.161.50]) by smtp.gmail.com with ESMTPSA id bt4-20020ac86904000000b00304febfc2ddsm14585qtb.56.2022.06.07.05.32.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 05:32:06 -0700 (PDT) Message-ID: <72b2c30861566c366deff686e965db53694e8f8f.camel@redhat.com> Subject: Re: [PATCH 1/7] x86/cpu: Add CPUID feature bit for VNMI From: Maxim Levitsky To: Santosh Shukla , Paolo Bonzini Cc: Sean Christopherson , Vitaly Kuznetsov , Jim Mattson , Joerg Roedel , Tom Lendacky , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Date: Tue, 07 Jun 2022 15:32:03 +0300 In-Reply-To: <20220602142620.3196-2-santosh.shukla@amd.com> References: <20220602142620.3196-1-santosh.shukla@amd.com> <20220602142620.3196-2-santosh.shukla@amd.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.40.4 (3.40.4-2.fc34) MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2022-06-02 at 19:56 +0530, Santosh Shukla wrote: > VNMI feature allows the hypervisor to inject NMI into the guest w/o > using Event injection mechanism, The benefit of using VNMI over the > event Injection that does not require tracking the Guest's NMI state and > intercepting the IRET for the NMI completion. VNMI achieves that by > exposing 3 capability bits in VMCB intr_cntrl which helps with > virtualizing NMI injection and NMI_Masking. > > The presence of this feature is indicated via the CPUID function > 0x8000000A_EDX[25]. > > Signed-off-by: Santosh Shukla > --- >  arch/x86/include/asm/cpufeatures.h | 1 + >  1 file changed, 1 insertion(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 393f2bbb5e3a..c8775b25856b 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -346,6 +346,7 @@ >  #define X86_FEATURE_V_VMSAVE_VMLOAD    (15*32+15) /* Virtual VMSAVE VMLOAD */ >  #define X86_FEATURE_VGIF               (15*32+16) /* Virtual GIF */ >  #define X86_FEATURE_V_SPEC_CTRL                (15*32+20) /* Virtual SPEC_CTRL */ > +#define X86_FEATURE_V_NMI              (15*32+25) /* Virtual NMI */ >  #define X86_FEATURE_SVME_ADDR_CHK      (15*32+28) /* "" SVME addr check */ >   >  /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */ I also think that AMD should publish some sort of a 'future ISA' spec like Intel does, so that we could avoid mistakes in reviweing the code. Other than that: Reviewed-by: Maxim Levitsky Best regards, Maxim Levitsky