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Wed, 24 Jun 2026 00:36:31 -0700 (PDT) X-Received: by 2002:a05:620a:29d2:b0:915:c76f:26e0 with SMTP id af79cd13be357-9277e739cffmr377965585a.18.1782286590436; Wed, 24 Jun 2026 00:36:30 -0700 (PDT) Received: from [192.168.0.172] ([49.205.250.204]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c0c5ef8acaesm616235666b.27.2026.06.24.00.36.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 24 Jun 2026 00:36:29 -0700 (PDT) Message-ID: <72b8e47e-df95-46f4-8c42-91f07a328065@oss.qualcomm.com> Date: Wed, 24 Jun 2026 13:06:19 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 09/16] media: iris: Add framework support for AR50_LITE video core To: Dmitry Baryshkov , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vishnu Reddy Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Dikshita Agarwal References: <20260616-iris-ar50lt-v5-0-583b42770b6a@oss.qualcomm.com> <20260616-iris-ar50lt-v5-9-583b42770b6a@oss.qualcomm.com> Content-Language: en-US From: Vikash Garodia In-Reply-To: <20260616-iris-ar50lt-v5-9-583b42770b6a@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI0MDA2MSBTYWx0ZWRfXwJ5mPgaUhnuj XcFCulIS76YDTWL4bb6mXd8/NpJeFDy3pcXprYDkwlHTav9NzgYLmYV05o+tyPDagf6x+wES10q jUjPCvt4ES599sOrFpqb/GjM1cZkPsU= X-Proofpoint-GUID: qrdFQ4EO7nZJllE80TLGEYvqcgeampOW X-Proofpoint-ORIG-GUID: qrdFQ4EO7nZJllE80TLGEYvqcgeampOW X-Authority-Analysis: v=2.4 cv=DbUnbPtW c=1 sm=1 tr=0 ts=6a3b88ff cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=9U17wRWtyhLDe7ZN7ogbJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=Lu1VWoxmIdvzX4MP_goA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI0MDA2MSBTYWx0ZWRfX4Gx2/ibW4vA1 WFdm0b1HH3XGZFWFocXt10Z4SDtaG8GKXeHxG5zYC7pQk/3JxVKiJQbqHGN5FQ/9XyYqVouxoEQ 3sKCWJe/+u+rPVa5zIXbhsKU+SxvivoU1CVH5kdolK566TexVLE8i6/Mr5R8qpuZzR0TiuBJ8Km 4LgDHv+4GTgHzB70RyjMwTVLBaMDgGpYP+xHX1E5Tb2pD/ooEshFoMcayOb2foSGazh7P32a3oS heBfxqIxVIZg7l/jFDJIge4oC4+o3JrHlwjDC5O9STumeGvhxDwFMCmbZFj1009DZ3YbwLMOwe+ y5MlqQRJUAtDOTuL+/tgJNrvi7yAtpKot9NIsBGdBN1lTaYjt2hYsM+XX6a++NP9MorhIYISdLK 2B1UgWm5L2hY701evAI8LzfB0L2ughze1dPEn5cT7H84wN4ldA4P+hBiIPWtzcIzOjO9zGrxMoH zhxE1zFxaCAFU1I1JEw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-24_02,2026-06-23_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 phishscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606240061 On 6/16/2026 5:34 AM, Dmitry Baryshkov wrote: > From: Dikshita Agarwal > > Add power sequence for ar5lt core. > Add register handling for ar50lt by hooking up vpu op with ar50lt > specific implemtation or resue from earlier generation wherever > feasible. > > Signed-off-by: Dikshita Agarwal > Signed-off-by: Dmitry Baryshkov > --- > drivers/media/platform/qcom/iris/Makefile | 1 + > .../platform/qcom/iris/iris_platform_common.h | 2 + > drivers/media/platform/qcom/iris/iris_vpu2.c | 28 +---- > drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c | 130 +++++++++++++++++++++ > drivers/media/platform/qcom/iris/iris_vpu_common.c | 29 ++++- > drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 + > 6 files changed, 164 insertions(+), 28 deletions(-) > > diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile > index 48e415cbc439..f1b204b95694 100644 > --- a/drivers/media/platform/qcom/iris/Makefile > +++ b/drivers/media/platform/qcom/iris/Makefile > @@ -26,6 +26,7 @@ qcom-iris-objs += iris_buffer.o \ > iris_vpu2.o \ > iris_vpu3x.o \ > iris_vpu4x.o \ > + iris_vpu_ar50lt.o \ > iris_vpu_buffer.o \ > iris_vpu_common.o \ > > diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h > index accc1627defd..6a189489369f 100644 > --- a/drivers/media/platform/qcom/iris/iris_platform_common.h > +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h > @@ -74,6 +74,7 @@ enum platform_clk_type { > IRIS_VPP0_HW_CLK, > IRIS_VPP1_HW_CLK, > IRIS_APV_HW_CLK, > + IRIS_THROTTLE_CLK, As we extend the common enum for (one off probably) SOC specific entries, should we bring in the changes to migrate this to per block clock data, something which was done here [1] ? [1] https://lore.kernel.org/linux-media/20260610-glymur-v8-6-1c79b9d51fc0@oss.qualcomm.com/ > }; > > struct platform_clk_data { > @@ -315,6 +316,7 @@ struct iris_platform_data { > u32 tz_cp_config_data_size; > u32 num_vpp_pipe; > bool no_aon; > + bool no_rpmh; > u32 wd_intr_mask; > u32 icc_ib_multiplier; > u32 max_session_count; > diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/platform/qcom/iris/iris_vpu2.c > index dd2eeae0d9eb..5419a5096b00 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu2.c > +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c > @@ -12,38 +12,12 @@ > > #include "iris_vpu_register_defines.h" > > -static u64 iris_vpu2_calc_freq(struct iris_inst *inst, size_t data_size) > -{ > - struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps; > - struct v4l2_format *inp_f = inst->fmt_src; > - u32 mbs_per_second, mbpf, height, width; > - unsigned long vpp_freq, vsp_freq; > - u32 fps = inst->frame_rate; > - > - width = max(inp_f->fmt.pix_mp.width, inst->crop.width); > - height = max(inp_f->fmt.pix_mp.height, inst->crop.height); > - > - mbpf = NUM_MBS_PER_FRAME(height, width); > - mbs_per_second = mbpf * fps; > - > - vpp_freq = mbs_per_second * caps->mb_cycles_vpp; > - > - /* 21 / 20 is overhead factor */ > - vpp_freq += vpp_freq / 20; > - vsp_freq = mbs_per_second * caps->mb_cycles_vsp; > - > - /* 10 / 7 is overhead factor */ > - vsp_freq += ((fps * data_size * 8) * 10) / 7; > - > - return max(vpp_freq, vsp_freq); > -} > - > const struct vpu_ops iris_vpu2_ops = { > .power_off_hw = iris_vpu_power_off_hw, > .power_on_hw = iris_vpu_power_on_hw, > .power_off_controller = iris_vpu_power_off_controller, > .power_on_controller = iris_vpu_power_on_controller, > - .calc_freq = iris_vpu2_calc_freq, > + .calc_freq = iris_vpu2_calculate_frequency, > .set_hwmode = iris_vpu_set_hwmode, > .set_preset_registers = iris_vpu_set_preset_registers, > .interrupt_init = iris_vpu_interrupt_init, > diff --git a/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c b/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c > new file mode 100644 > index 000000000000..e084a5b49f2e > --- /dev/null > +++ b/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c > @@ -0,0 +1,130 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include > +#include > +#include > + > +#include "iris_instance.h" > +#include "iris_vpu_common.h" > + > +#include "iris_vpu_register_defines.h" > + > +#define WRAPPER_INTR_MASK_A2HVCODEC_BMSK_AR50LT BIT(3) > + > +#define WRAPPER_VCODEC0_CLOCK_CONFIG_AR50LT 0xb0080 > + > +#define CPU_CS_VCICMD 0xa0020 > +#define CPU_CS_VCICMD_ARP_OFF 0x1 > + > +static void iris_vpu_ar50lt_set_preset_registers(struct iris_core *core) > +{ > + writel(0x0, core->reg_base + WRAPPER_VCODEC0_CLOCK_CONFIG_AR50LT); > +} > + > +static void iris_vpu_ar50lt_interrupt_init(struct iris_core *core) > +{ > + writel(WRAPPER_INTR_MASK_A2HVCODEC_BMSK_AR50LT, core->reg_base + WRAPPER_INTR_MASK); > +} > + > +static void iris_vpu_ar50lt_disable_arp(struct iris_core *core) > +{ > + writel(CPU_CS_VCICMD_ARP_OFF, core->reg_base + CPU_CS_VCICMD); > +} > + > +static int iris_vpu_ar50lt_power_off_controller(struct iris_core *core) > +{ > + iris_disable_unprepare_clock(core, IRIS_AHB_CLK); > + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); > + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); > + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); > + > + return 0; > +} > + > +static void iris_vpu_ar50lt_power_off_hw(struct iris_core *core) > +{ > + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false); > + iris_disable_unprepare_clock(core, IRIS_THROTTLE_CLK); > + iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); > + iris_disable_unprepare_clock(core, IRIS_HW_CLK); > + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); > +} > + > +static int iris_vpu_ar50lt_power_on_controller(struct iris_core *core) > +{ > + int ret; > + > + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); > + if (ret) > + return ret; > + > + ret = iris_prepare_enable_clock(core, IRIS_CTRL_CLK); > + if (ret) > + goto err_disable_power; > + > + ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK); > + if (ret && ret != -ENOENT) > + goto err_disable_ctrl_clock; > + > + ret = iris_prepare_enable_clock(core, IRIS_AHB_CLK); > + if (ret) > + goto err_disable_axi_clock; > + > + return 0; > + > +err_disable_axi_clock: > + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); > +err_disable_ctrl_clock: > + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); > +err_disable_power: > + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); > + > + return ret; > +} > + > +static int iris_vpu_ar50lt_power_on_hw(struct iris_core *core) > +{ > + int ret; > + > + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); > + if (ret) > + return ret; > + > + ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); > + if (ret) > + goto err_disable_power; > + > + ret = iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK); > + if (ret) > + goto err_disable_hw_clock; > + > + ret = iris_prepare_enable_clock(core, IRIS_THROTTLE_CLK); > + if (ret) > + goto err_disable_hw_ahb_clock; > + > + return 0; ...lot of these per soc specific clock handling would be removed. Regards, Vikash