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[91.159.24.186]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a2a064c187sm243911e87.27.2026.03.25.18.46.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 25 Mar 2026 18:46:37 -0700 (PDT) Message-ID: <72ef6c9e-feb6-4e57-b8cc-7801bd748698@linaro.org> Date: Thu, 26 Mar 2026 03:46:27 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema To: Bryan O'Donoghue , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong Cc: Bryan O'Donoghue , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260326-x1e-csi2-phy-v5-0-0c0fc7f5c01b@linaro.org> <20260326-x1e-csi2-phy-v5-1-0c0fc7f5c01b@linaro.org> From: Vladimir Zapolskiy In-Reply-To: <20260326-x1e-csi2-phy-v5-1-0c0fc7f5c01b@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 3/26/26 03:04, Bryan O'Donoghue wrote: > Add a base schema initially compatible with x1e80100 to describe MIPI CSI2 > PHY devices. > > The hardware can support both CPHY, DPHY and a special split-mode DPHY. We > capture those modes as: > > - PHY_QCOM_CSI2_MODE_DPHY > - PHY_QCOM_CSI2_MODE_CPHY > - PHY_QCOM_CSI2_MODE_SPLIT_DPHY Distinction between PHY_QCOM_CSI2_MODE_DPHY and PHY_QCOM_CSI2_MODE_SPLIT_DPHY is 1) insufficient in just this simplistic form, because the assignment of particular lanes is also needed, 2) and under the assumption that the lane mapping is set somewhere else, then there should be no difference between PHY_QCOM_CSI2_MODE_{DPHY,SPLIT_DPHY}, it's just DPHY, and the subtype is deductible from data-lanes property on the consumer side. So far the rationale is unclear, why anything above regular PHY_TYPE_DPHY and PHY_TYPE_CPHY is needed here, those two are sufficient. > > The CSIPHY devices have their own pinouts on the SoC as well as their own > individual voltage rails. > > The need to model voltage rails on a per-PHY basis leads us to define > CSIPHY devices as individual nodes. > > Two nice outcomes in terms of schema and DT arise from this change. > > 1. The ability to define on a per-PHY basis voltage rails. > 2. The ability to require those voltage. > > We have had a complete bodge upstream for this where a single set of > voltage rail for all CSIPHYs has been buried inside of CAMSS. > > Much like the I2C bus which is dedicated to Camera sensors - the CCI bus in > CAMSS parlance, the CSIPHY devices should be individually modelled. > > Signed-off-by: Bryan O'Donoghue > --- > .../bindings/phy/qcom,x1e80100-csi2-phy.yaml | 130 +++++++++++++++++++++ > include/dt-bindings/phy/phy-qcom-mipi-csi2.h | 15 +++ > 2 files changed, 145 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml > new file mode 100644 > index 0000000000000..63114151104b4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml > @@ -0,0 +1,130 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,x1e80100-csi2-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm CSI2 PHY > + > +maintainers: > + - Bryan O'Donoghue > + > +description: > + Qualcomm MIPI CSI2 C-PHY/D-PHY combination PHY. Connects MIPI CSI2 sensors > + to Qualcomm's Camera CSI Decoder. The PHY supports both C-PHY and D-PHY > + modes. > + > +properties: > + compatible: > + const: qcom,x1e80100-csi2-phy > + > + reg: > + maxItems: 1 > + > + "#phy-cells": > + const: 1 > + description: > + The single cell specifies the PHY operating mode. > + See include/dt-bindings/phy/phy-qcom-mipi-csi2.h for valid values. include/dt-bindings/phy/phy.h should be good enough as it's stated above. > + > + clocks: > + maxItems: 2 > + > + clock-names: > + items: > + - const: core > + - const: timer > + > + interrupts: > + maxItems: 1 > + > + operating-points-v2: > + maxItems: 1 > + > + power-domains: > + items: > + - description: MXC or MXA voltage rail > + - description: MMCX voltage rail > + > + power-domain-names: > + items: > + - const: mx > + - const: mmcx > + > + vdda-0p9-supply: > + description: Phandle to a 0.9V regulator supply to a PHY. > + > + vdda-1p2-supply: > + description: Phandle to 1.2V regulator supply to a PHY. > + > +required: > + - compatible > + - reg > + - "#phy-cells" > + - clocks > + - clock-names > + - interrupts > + - operating-points-v2 > + - power-domains > + - power-domain-names > + - vdda-0p9-supply > + - vdda-1p2-supply > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + > + csiphy4: csiphy@ace4000 { > + compatible = "qcom,x1e80100-csi2-phy"; > + reg = <0x0ace4000 0x2000>; > + #phy-cells = <1>; > + > + clocks = <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; > + clock-names = "core", > + "timer"; > + > + operating-points-v2 = <&csiphy_opp_table>; > + > + interrupts = ; > + > + power-domains = <&rpmhpd RPMHPD_MX>, > + <&rpmhpd RPMHPD_MMCX>; > + power-domain-names = "mx", > + "mmcx"; > + > + vdda-0p9-supply = <&vreg_l2c_0p8>; > + vdda-1p2-supply = <&vreg_l1c_1p2>; > + }; > + > + csiphy_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_low_svs_d1>, > + <&rpmhpd_opp_low_svs_d1>; > + }; > + > + opp-400000000 { > + opp-hz = /bits/ 64 <400000000>; > + required-opps = <&rpmhpd_opp_low_svs>, > + <&rpmhpd_opp_low_svs>; > + }; > + > + opp-480000000 { > + opp-hz = /bits/ 64 <480000000>; > + required-opps = <&rpmhpd_opp_low_svs>, > + <&rpmhpd_opp_low_svs>; > + }; > + }; > + > + isp@acb7000 { > + phys = <&csiphy4 PHY_QCOM_CSI2_MODE_DPHY>; > + }; This example is incomplete in sense that it does not include CAMSS CSIPHY IP hardware configuration in whole. > diff --git a/include/dt-bindings/phy/phy-qcom-mipi-csi2.h b/include/dt-bindings/phy/phy-qcom-mipi-csi2.h > new file mode 100644 > index 0000000000000..fa48fd75c58d8 > --- /dev/null > +++ b/include/dt-bindings/phy/phy-qcom-mipi-csi2.h > @@ -0,0 +1,15 @@ > +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ > +/* > + * Qualcomm MIPI CSI2 PHY constants > + * > + * Copyright (C) 2026 Linaro Limited > + */ > + > +#ifndef __DT_BINDINGS_PHY_MIPI_CSI2__ > +#define __DT_BINDINGS_PHY_MIPI_CSI2__ > + > +#define PHY_QCOM_CSI2_MODE_DPHY 0 > +#define PHY_QCOM_CSI2_MODE_CPHY 1 > +#define PHY_QCOM_CSI2_MODE_SPLIT_DPHY 2 > + > +#endif /* __DT_BINDINGS_PHY_MIPI_CSI2__ */ > -- Best wishes, Vladimir