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R. A. Prado" To: Harry Wentland , Louis Chauvet , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Simona Vetter Date: Mon, 29 Sep 2025 12:00:40 -0400 In-Reply-To: <52cce852-f4fb-4692-9318-1602fe878644@amd.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> <20250917-mtk-post-blend-color-pipeline-v2-5-ac4471b44758@collabora.com> <52cce852-f4fb-4692-9318-1602fe878644@amd.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-2+b1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ZohoMailClient: External X-ZohoMail-Owner: <7307e84f9e4b0a8c67b82f7234f90bf83f201037.camel@collabora.com>+zmo_0_nfraprado@collabora.com On Mon, 2025-09-29 at 05:40 -0400, Harry Wentland wrote: >=20 >=20 > On 2025-09-19 08:42, Louis Chauvet wrote: > >=20 > >=20 > > Le 18/09/2025 =C3=A0 02:43, N=C3=ADcolas F. R. A. Prado a =C3=A9crit=C2= =A0: > > > Add a new cap that drivers can set to signal they support post- > > > blend > > > color pipelines. > > >=20 > > > Signed-off-by: N=C3=ADcolas F. R. A. Prado > >=20 > > Reviewed-by: Louis Chauvet > >=20 > > > --- > > > =C2=A0 drivers/gpu/drm/drm_ioctl.c | 3 +++ > > > =C2=A0 include/drm/drm_drv.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 6 = ++++++ > > > =C2=A0 include/uapi/drm/drm.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 6 +++++= + > > > =C2=A0 3 files changed, 15 insertions(+) > > >=20 > > > diff --git a/drivers/gpu/drm/drm_ioctl.c > > > b/drivers/gpu/drm/drm_ioctl.c > > > index=20 > > > ff193155129e7e863888d8958458978566b144f8..01592d10e3465ddceddef94 > > > bc417f98d3ec12087 100644 > > > --- a/drivers/gpu/drm/drm_ioctl.c > > > +++ b/drivers/gpu/drm/drm_ioctl.c > > > @@ -304,6 +304,9 @@ static int drm_getcap(struct drm_device *dev, > > > void=20 > > > *data, struct drm_file *file_ > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 req->value =3D= drm_core_check_feature(dev, DRIVER_ATOMIC) > > > && > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dev->mode_config.async_page_flip; > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break; > > > +=C2=A0=C2=A0=C2=A0 case DRM_CAP_POST_BLEND_COLOR_PIPELINE: > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 req->value =3D drm_core_c= heck_feature(dev,=20 > > > DRIVER_POST_BLEND_COLOR_PIPELINE); > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break; > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 default: > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return -EINVAL= ; > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } > > > diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h > > > index=20 > > > 42fc085f986dee9261f8b08c4fc7d93b8d6d9769..6b0f4904e69766232283d43 > > > 0c2540d30afef850f 100644 > > > --- a/include/drm/drm_drv.h > > > +++ b/include/drm/drm_drv.h > > > @@ -122,6 +122,12 @@ enum drm_driver_feature { > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * the cursor planes to work corr= ectly). > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 */ > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 DRIVER_CURSOR_HOTSPOT=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D BIT(9), > > > +=C2=A0=C2=A0=C2=A0 /** > > > +=C2=A0=C2=A0=C2=A0=C2=A0 * @DRIVER_POST_BLEND_COLOR_PIPELINE: > > > +=C2=A0=C2=A0=C2=A0=C2=A0 * > > > +=C2=A0=C2=A0=C2=A0=C2=A0 * Driver supports post-blend color pipeline= . > > > +=C2=A0=C2=A0=C2=A0=C2=A0 */ > > > +=C2=A0=C2=A0=C2=A0 DRIVER_POST_BLEND_COLOR_PIPELINE=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D BIT(10), >=20 > Is this to let userspace know that the driver supports a > post-blending color pipeline? Why couldn't userspace simply > check whether crtc objects have "Color Pipeline" properties? It is, and yes userspace could figure it out that way, though since the property is only exposed after the client cap is set, it requires a more involved setup: set the client cap, check for the property, if not present unset the client cap. With the driver cap introduced here, setting the client cap would fail in the first place if the driver cap is not set, so in this case userspace just tries to set the client cap, if it succeeds it knows it can use color pipelines, if it fails it knows to use the legacy color properties. --=20 Thanks, N=C3=ADcolas >=20 > Harry >=20 > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* IMPORTANT: Below are all the legacy= flags, add new ones=20 > > > above. */ > > > diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h > > > index=20 > > > 27cc159c1d275c7a7fe057840ef792f30a582bb7..c6c53e57958e951204154ce > > > 41a69696a6876f0e8 100644 > > > --- a/include/uapi/drm/drm.h > > > +++ b/include/uapi/drm/drm.h > > > @@ -812,6 +812,12 @@ struct drm_gem_change_handle { > > > =C2=A0=C2=A0 * commits. > > > =C2=A0=C2=A0 */ > > > =C2=A0 #define DRM_CAP_ATOMIC_ASYNC_PAGE_FLIP=C2=A0=C2=A0=C2=A0 0x15 > > > +/** > > > + * DRM_CAP_POST_BLEND_COLOR_PIPELINE > > > + * > > > + * If set to 1, the driver supports post-blend color pipelines. > > > + */ > > > +#define DRM_CAP_POST_BLEND_COLOR_PIPELINE=C2=A0=C2=A0=C2=A0 0x16 > > > =C2=A0 /* DRM_IOCTL_GET_CAP ioctl argument type */ > > > =C2=A0 struct drm_get_cap { > > >=20 > >=20