From: Jessica Zhang <quic_jesszhan@quicinc.com>
To: Dmitry Baryshkov <lumag@kernel.org>,
Rob Clark <robdclark@gmail.com>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>
Cc: <linux-arm-msm@vger.kernel.org>,
<dri-devel@lists.freedesktop.org>,
<freedreno@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>,
"Neil Armstrong" <neil.armstrong@linaro.org>
Subject: Re: [PATCH v3 4/8] drm/msm/dpu: use single CTL if it is the only CTL returned by RM
Date: Mon, 28 Apr 2025 16:57:40 -0700 [thread overview]
Message-ID: <73258107-4a5b-4917-ab0b-81ff4cc96072@quicinc.com> (raw)
In-Reply-To: <20250307-dpu-active-ctl-v3-4-5d20655f10ca@linaro.org>
On 3/6/2025 10:24 PM, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> On DPU >= 5.0 CTL blocks were reworked in order to support using a
> single CTL for all outputs. In preparation of reworking the RM code to
> return single CTL make sure that dpu_encoder can cope with that.
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 0eed93a4d056beda6b54c0d20f027a53c84f67db..b5e8ba592d8af298a52924d34a573d4f9e05c476 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -1247,7 +1247,11 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
> return;
> }
>
> - phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : NULL;
> + /* Use first (and only) CTL if active CTLs are supported */
> + if (num_ctl == 1)
> + phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[0]);
> + else
> + phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : NULL;
> if (!phys->hw_ctl) {
> DPU_ERROR_ENC(dpu_enc,
> "no ctl block assigned at idx: %d\n", i);
>
next prev parent reply other threads:[~2025-04-28 23:57 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-07 6:24 [PATCH v3 0/8] drm/msm/dpu: improve CTL handling on DPU >= 5.0 platforms Dmitry Baryshkov
2025-03-07 6:24 ` [PATCH v3 1/8] drm/msm/dpu: don't overwrite CTL_MERGE_3D_ACTIVE register Dmitry Baryshkov
2025-04-28 19:02 ` Jessica Zhang
2025-05-06 8:47 ` Marijn Suijten
2025-03-07 6:24 ` [PATCH v3 2/8] drm/msm/dpu: program master INTF value Dmitry Baryshkov
2025-04-28 22:48 ` Jessica Zhang
2025-03-07 6:24 ` [PATCH v3 3/8] drm/msm/dpu: pass master interface to CTL configuration Dmitry Baryshkov
2025-04-29 23:48 ` Jessica Zhang
2025-03-07 6:24 ` [PATCH v3 4/8] drm/msm/dpu: use single CTL if it is the only CTL returned by RM Dmitry Baryshkov
2025-04-28 23:57 ` Jessica Zhang [this message]
2025-03-07 6:24 ` [PATCH v3 5/8] drm/msm/dpu: don't select single flush for active CTL blocks Dmitry Baryshkov
2025-04-30 0:02 ` Jessica Zhang
2025-03-07 6:24 ` [PATCH v3 6/8] drm/msm/dpu: allocate single CTL for DPU >= 5.0 Dmitry Baryshkov
2025-04-30 0:35 ` Jessica Zhang
2025-03-07 6:24 ` [PATCH v3 7/8] drm/msm/dpu: remove DPU_CTL_SPLIT_DISPLAY from CTL blocks on " Dmitry Baryshkov
2025-04-30 0:42 ` Jessica Zhang
2025-03-07 6:24 ` [PATCH v3 8/8] drm/msm/dpu: drop now-unused condition for has_legacy_ctls Dmitry Baryshkov
2025-04-30 0:42 ` Jessica Zhang
2025-05-04 16:13 ` [PATCH v3 0/8] drm/msm/dpu: improve CTL handling on DPU >= 5.0 platforms Dmitry Baryshkov
2025-05-19 10:58 ` Dmitry Baryshkov
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