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Thu, 26 Sep 2024 06:14:26 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48Q6EP68021246 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Sep 2024 06:14:25 GMT Received: from [10.217.219.207] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 25 Sep 2024 23:14:23 -0700 Message-ID: <732bdb12-a52b-4abe-8edb-afed44406011@quicinc.com> Date: Thu, 26 Sep 2024 11:44:20 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/1] i2c: qcom-geni: Support systems with 32MHz serial engine clock To: Manikanta Mylavarapu , , , , CC: , References: <20240926034304.3565278-1-quic_mmanikan@quicinc.com> Content-Language: en-US From: Mukesh Kumar Savaliya In-Reply-To: <20240926034304.3565278-1-quic_mmanikan@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 7zSXD4aCOa117VjYjWKgErTDL1HSFwrb X-Proofpoint-GUID: 7zSXD4aCOa117VjYjWKgErTDL1HSFwrb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 spamscore=0 lowpriorityscore=0 adultscore=0 mlxscore=0 suspectscore=0 malwarescore=0 phishscore=0 impostorscore=0 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409260039 Hi Manikanta, My suggestion: i2c: qcom-geni: Support systems with 32MHz serial engine clock [Derive i2c clock from 32MHz Sourced clock] On 9/26/2024 9:13 AM, Manikanta Mylavarapu wrote: > In existing socs, I2C serial engine is sourced from XO (19.2MHz). > Where as in IPQ5424, I2C serial engine is sourced from GPLL0 (32MHz). > > The existing map table is based on 19.2MHz. This patch incorporate incorporate/s/incorporates > the clock map table to derive the SCL clock from the 32MHz source > clock frequency. > > Signed-off-by: Manikanta Mylavarapu > --- > Changes in v2: > - Dropped IPQ5424 from the commit title > - Added else part to assign geni_i2c_clk_map_19p2mhz to itr > - Dropped MHZ macro and used HZ_PER_MHZ macro > - Expanded SE to serial engine > - Added the reason for 32MHz clock in commit message > > drivers/i2c/busses/i2c-qcom-geni.c | 19 ++++++++++++++++--- > 1 file changed, 16 insertions(+), 3 deletions(-) > > diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c > index 212336f724a6..22f2a0d83641 100644 > --- a/drivers/i2c/busses/i2c-qcom-geni.c > +++ b/drivers/i2c/busses/i2c-qcom-geni.c > @@ -16,6 +16,7 @@ > #include > #include > #include > +#include > > #define SE_I2C_TX_TRANS_LEN 0x26c > #define SE_I2C_RX_TRANS_LEN 0x270 > @@ -146,18 +147,30 @@ struct geni_i2c_clk_fld { > * clk_freq_out = t / t_cycle > * source_clock = 19.2 MHz > */ > -static const struct geni_i2c_clk_fld geni_i2c_clk_map[] = { > +static const struct geni_i2c_clk_fld geni_i2c_clk_map_19p2mhz[] = { > {KHZ(100), 7, 10, 11, 26}, > {KHZ(400), 2, 5, 12, 24}, > {KHZ(1000), 1, 3, 9, 18}, > }; > > +/* source_clock = 32 MHz */ > +static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = { > + {KHZ(100), 7, 14, 18, 40}, > + {KHZ(400), 4, 3, 11, 20}, > + {KHZ(1000), 4, 3, 6, 15}, > +}; > + > static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) > { > int i; > - const struct geni_i2c_clk_fld *itr = geni_i2c_clk_map; > + const struct geni_i2c_clk_fld *itr; > + > + if (clk_get_rate(gi2c->se.clk) == 32 * HZ_PER_MHZ) > + itr = geni_i2c_clk_map_32mhz; > + else > + itr = geni_i2c_clk_map_19p2mhz; > > - for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) { > + for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map_19p2mhz); i++, itr++) { > if (itr->clk_freq_out == gi2c->clk_freq_out) { > gi2c->clk_fld = itr; > return 0;