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Fri, 21 Aug 2026 15:16:04 -0700 (PDT) Message-ID: <734e126e531e320e281361579ba8fb190bff032f.camel@redhat.com> Subject: Re: [PATCH v2 09/10] drm/nouveau/dispnv50: program pixel clocks above 2.147GHz on GB20x From: lyude@redhat.com To: Mohamed Ahmed , linux-kernel@vger.kernel.org Cc: dri-devel@lists.freedesktop.org, Danilo Krummrich , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Mary Guillemard , nouveau@lists.freedesktop.org Date: Fri, 21 Aug 2026 18:16:03 -0400 In-Reply-To: <20260820164929.17117-10-mohamedahmedegypt2001@gmail.com> References: <20260820164929.17117-1-mohamedahmedegypt2001@gmail.com> <20260820164929.17117-10-mohamedahmedegypt2001@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.3 (3.58.3-1.fc43) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Reviewed-by: Lyude Paul On Thu, 2026-08-20 at 20:49 +0400, Mohamed Ahmed wrote: > The HEAD_SET_PIXEL_CLOCK_FREQUENCY(_MAX) methods carry only 31 HERTZ > bits. Starting with C97D the upper bits live in separate > HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI(_MAX) methods, which nouveau never > programmed and headca7d_mode() computed m->clock * 1000 into the 31- > bit > field. NVVAL's mask then silently truncates anything past 2^31 Hz, > which > means that every mode scanned out at pclk modulo 2^31. >=20 > No mode nouveau can currently commit crosses the boundary (an > uncompressed HDMI FRL mode tops out around 1.78GHz at 8bpc), but this > is > a prerequisite for the upcoming DSC work, which makes 2.147GHz+ modes > reachable. >=20 > Program the full value split across the low and HI methods, exactly > as OpenRM's EvoSetRasterParams9() does (nvkms-evo4.c, 31-bit low word > plus the 4 HI HERTZ bits, giving 35 bits of range). >=20 > Signed-off-by: Mohamed Ahmed > --- > =C2=A0drivers/gpu/drm/nouveau/dispnv50/headca7d.c=C2=A0=C2=A0 | 21 ++++++= ++++++++++- > -- > =C2=A0.../drm/nouveau/include/nvhw/class/clca7d.h=C2=A0=C2=A0 |=C2=A0 4 += +++ > =C2=A02 files changed, 22 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/gpu/drm/nouveau/dispnv50/headca7d.c > b/drivers/gpu/drm/nouveau/dispnv50/headca7d.c > index eeaeb15aa664..678cbc78ca9f 100644 > --- a/drivers/gpu/drm/nouveau/dispnv50/headca7d.c > +++ b/drivers/gpu/drm/nouveau/dispnv50/headca7d.c > @@ -219,10 +219,11 @@ headca7d_mode(struct nv50_head *head, struct > nv50_head_atom *asyh) > =C2=A0{ > =C2=A0 struct nvif_push *push =3D &head->disp->core->chan.push; > =C2=A0 struct nv50_head_mode *m =3D &asyh->mode; > + const u64 hz =3D (u64)m->clock * 1000; > =C2=A0 const int i =3D head->base.index; > =C2=A0 int ret; > =C2=A0 > - ret =3D PUSH_WAIT(push, 11); > + ret =3D PUSH_WAIT(push, 14); > =C2=A0 if (ret) > =C2=A0 return ret; > =C2=A0 > @@ -245,11 +246,25 @@ headca7d_mode(struct nv50_head *head, struct > nv50_head_atom *asyh) > =C2=A0 PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL(i), > =C2=A0 =C2=A0 NVDEF(NVCA7D, HEAD_SET_CONTROL, STRUCTURE, > PROGRESSIVE)); > =C2=A0 > + /* The FREQUENCY methods carry only 31 HERTZ bits; the upper > bits > + * of anything past 2.147GHz live in the HI methods > + * (EvoSetRasterParams9()). Truncating would scan out at > pclk modulo 2^31. > + */ > =C2=A0 PUSH_MTHD(push, NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i), > - =C2=A0 NVVAL(NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, > HERTZ, m->clock * 1000)); > + =C2=A0 NVVAL(NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, > HERTZ, > + (u32)(hz & 0x7fffffff))); > =C2=A0 > =C2=A0 PUSH_MTHD(push, NVCA7D, > HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i), > - =C2=A0 NVVAL(NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, > HERTZ, m->clock * 1000)); > + =C2=A0 NVVAL(NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, > HERTZ, > + (u32)(hz & 0x7fffffff))); > + > + PUSH_MTHD(push, NVCA7D, > HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI(i), > + =C2=A0 NVVAL(NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI, > HERTZ, > + (u32)(hz >> 31)), > + > + HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_MA > X(i), > + =C2=A0 NVVAL(NVCA7D, > HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_MAX, HERTZ, > + (u32)(hz >> 31))); > =C2=A0 > =C2=A0 return 0; > =C2=A0} > diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/clca7d.h > b/drivers/gpu/drm/nouveau/include/nvhw/class/clca7d.h > index 0fec6fc21d44..5754878ddc69 100644 > --- a/drivers/gpu/drm/nouveau/include/nvhw/class/clca7d.h > +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/clca7d.h > @@ -734,6 +734,10 @@ > =C2=A0#define > NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 > =C2=A0=C2=A0 20:20 > =C2=A0#define > NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_DISABLE=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 > =C2=A0=C2=A0 (0x00000000) > =C2=A0#define > NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_ENABLE=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 > =C2=A0=C2=A0 (0x00000001) > +#define > NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI(a)=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 > =C2=A0=C2=A0 (0x000020C0 + (a)*0x00000800) > +#define > NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_HERTZ=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 > =C2=A0=C2=A0 3:0 > +#define > NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_MAX(a)=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 > =C2=A0=C2=A0 (0x000020C4 + (a)*0x00000800) > +#define > NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_MAX_HERTZ=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 > =C2=A0=C2=A0 3:0 > =C2=A0#define > NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_CRC(a)=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 > =C2=A0=C2=A0 (0x00002150 + (a)*0x00000800) > =C2=A0#define > NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_CRC_ADDRESS_HI=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 > =C2=A0=C2=A0 31:0 > =C2=A0#define > NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC(a)=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 > =C2=A0=C2=A0 (0x00002154 + (a)*0x00000800)