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Fri, 04 Jul 2025 01:51:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGjHONIzeZBcmHDs0wQAo/69TAD7L3QCa4R8AjRrd36Wfaj0nIqIpoFwuQZvSMwqbOAfbsgpw== X-Received: by 2002:a17:90b:4a81:b0:312:e279:9ccf with SMTP id 98e67ed59e1d1-31aac432867mr2650903a91.5.1751619109127; Fri, 04 Jul 2025 01:51:49 -0700 (PDT) Received: from [10.151.37.217] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31a9cc675absm4678341a91.19.2025.07.04.01.51.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Jul 2025 01:51:48 -0700 (PDT) Message-ID: <735a84f4-25b7-431e-9280-aed34e9254a1@oss.qualcomm.com> Date: Fri, 4 Jul 2025 14:21:44 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/7] dt-bindings: sram: qcom,imem: Document Qualcomm IPQ SoC's IMEM compatibles From: Kathiravan Thirumoorthy To: Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250702-imem-v1-0-12d49b1ceff0@oss.qualcomm.com> <20250702-imem-v1-1-12d49b1ceff0@oss.qualcomm.com> <37695966-1d7c-46c3-9717-30da4e8d1930@oss.qualcomm.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=H/Pbw/Yi c=1 sm=1 tr=0 ts=68679627 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=2Hie-wN6ZoqyeGEPU0sA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-ORIG-GUID: IHbD0ijia0oq25dpQJY4Np_SZ6faPXvy X-Proofpoint-GUID: IHbD0ijia0oq25dpQJY4Np_SZ6faPXvy X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzA0MDA2NyBTYWx0ZWRfX+RewwWPAUWjY zFJuCPmCLBji8HZ+95CzL1KQkVdaYbn4gEYXvY3IzUo2Js2x0TasRP7UKAzwUwsS3Em44MPFivG SMnyywfIYBbAhrE1jHlFqMcVthZIFkcB5BHVHOuTtGoF4FS2Q6L/Z1kLyxDtk0EbS3UQqJA+8Ak KoztjxQCQ3O9bN7nf9qNSYowWmiGCmeBjNEEhbRXdowlHzij2dMr3umKhiMY0H0Ra1rFD0nGJRz pUtsAqDdlgVGyKxnft2VIZ1UPkWfLOEp8/z9GHI3FvvU/ydDo2LDKf4Agoyu8QFWQpzs3ISxgA4 BKn0nUCr4nJTpCz/YT4uKiMZ3x12fD9EGrAWcZi5CUkodRH1cppsiV/ZUA0jVfMOcSzgULvn0aA nTMic1LZbKKXsw7PpvpHjxYOA7MNpf6lrTvN4Y/R6A1Ij2+QFjedI+2pEB+XwGMHpFcTTfg/ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-04_03,2025-07-02_04,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 mlxscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 bulkscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507040067 On 7/2/2025 4:29 PM, Kathiravan Thirumoorthy wrote: > > On 7/2/2025 4:18 PM, Krzysztof Kozlowski wrote: >> On 02/07/2025 12:46, Kathiravan Thirumoorthy wrote: >>> On 7/2/2025 3:49 PM, Krzysztof Kozlowski wrote: >>>> On 02/07/2025 12:17, Kathiravan Thirumoorthy wrote: >>>>> IMEM is present in the Qualcomm's IPQ SoCs as well. Document the >>>>> same. >>>>> >>>>> Signed-off-by: Kathiravan Thirumoorthy >>>>> >>>>> --- >>>>>    Documentation/devicetree/bindings/sram/qcom,imem.yaml | 6 ++++++ >>>>>    1 file changed, 6 insertions(+) >>>> Where is the changelog? This is not a v1. >>> This is the v1. The series[1] I pointed out describes only for the >>> IPQ5424 SoC. Since I have added few more SoCs, thought v1 is the >>> appropriate numbering. >>> >>> [1] >>> https://lore.kernel.org/linux-arm-msm/20250610-wdt_reset_reason-v5-0-2d2835160ab5@oss.qualcomm.com/ >>> >> But IPQ5424 is already there, so you reworked that patch. > Okay, so this should be V6? Let me drop the IPQ5424 support and send the V2. I hope that is fine. >> >> >>>>> diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml >>>>> b/Documentation/devicetree/bindings/sram/qcom,imem.yaml >>>>> index >>>>> 72d35e30c439ccf4901d937f838fe7c7a81f33b1..48e2f332e0e9fc9fa4147fa12d9c6c70a77fafda >>>>> 100644 >>>>> --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml >>>>> +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml >>>>> @@ -18,6 +18,12 @@ properties: >>>>>        items: >>>>>          - enum: >>>>>              - qcom,apq8064-imem >>>>> +          - qcom,ipq8074-imem >>>>> +          - qcom,ipq6018-imem >>>>> +          - qcom,ipq5018-imem >>>>> +          - qcom,ipq9574-imem >>>>> +          - qcom,ipq5332-imem >>>>> +          - qcom,ipq5424-imem >>>> Random order, no, follow existing style. This applies for every qcom >>>> binding and you received such feedbacks in the past. >>> Apologies — I arranged them based on the evolutionary order of SoCs. >> Where is such ordering documented? How is it expressed in your internal >> guideline for example? > I made the mistake unintentionally and apologized for the same! >> >> Best regards, >> Krzysztof