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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a1e82a5sm2171730766b.82.2025.08.12.01.58.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Aug 2025 01:58:42 -0700 (PDT) Message-ID: <7376d383-632d-42ce-bbdb-68c245d3879d@oss.qualcomm.com> Date: Tue, 12 Aug 2025 10:58:40 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] media: iris: vpu3x: Add MNoC low power handshake during hardware power-off To: Dikshita Agarwal , Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong References: <20250812-sm8650-power-sequence-fix-v1-1-a51e7f99c56c@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250812-sm8650-power-sequence-fix-v1-1-a51e7f99c56c@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA5MDAyNyBTYWx0ZWRfX2cRiuVYwKqX6 rv/jqm7JiwHOXV2p4q3rZ/fuRAzyHwPNMVH0EJbfjUrxGI8/e5Idl46wpflSW1oLjqs8UPD+10q KxM7bPm1O7W1Q2ZUA6Gpft3RIoi1Q0gVcf9FFv8T1+fl/5q/Qy5Vik37bCGR77UeGaz4hvLmRqy V6ex3S6yQW8DbWc6JDSCw2fYUxH/XFKKN36+2dvCmVpGRO/up9e9mEE7ZYPTSX2yAJvLGHXCmsN 6AzrkJRLZZVWpLH0u+Ae9Mf2NeR4Mb7c3estmgpr29mX10PtDbncjzew59svdXX4NA+AIbvkvAJ zsothBnCedVZyjvhLJMw6+8DdP81kQ7APeuEo0vxoaszkjxUiwrtiTp0u88vGa9UcbrBZ0M4WR5 DJ5+oDxi X-Authority-Analysis: v=2.4 cv=fvDcZE4f c=1 sm=1 tr=0 ts=689b0245 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=6ItR197CiITtoEHbj2UA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 94w2X9zCaYBqZfUwbIkim-70R8D5mICk X-Proofpoint-GUID: 94w2X9zCaYBqZfUwbIkim-70R8D5mICk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_04,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 priorityscore=1501 spamscore=0 suspectscore=0 clxscore=1015 phishscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508090027 On 8/12/25 9:48 AM, Dikshita Agarwal wrote: > Add the missing write to AON_WRAPPER_MVP_NOC_LPI_CONTROL before > reading the LPI status register. Introduce a handshake loop to ensure > MNoC enters low power mode reliably during VPU3 hardware power-off with > timeout handling. > > Signed-off-by: Dikshita Agarwal > --- > drivers/media/platform/qcom/iris/iris_vpu3x.c | 23 +++++++++++++++++++++-- > 1 file changed, 21 insertions(+), 2 deletions(-) > > diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c > index 9b7c9a1495ee2f51c60b1142b2ed4680ff798f0a..c2e6af575cbe4b3e3f2a019b24eecf3a5d469566 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c > +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c > @@ -110,6 +110,7 @@ static void iris_vpu3_power_off_hardware(struct iris_core *core) > static void iris_vpu33_power_off_hardware(struct iris_core *core) > { > u32 reg_val = 0, value, i; > + u32 count = 0; > int ret; > > if (iris_vpu3x_hw_power_collapsed(core)) > @@ -128,13 +129,31 @@ static void iris_vpu33_power_off_hardware(struct iris_core *core) > goto disable_power; > } > > + /* set MNoC to low power */ > + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); > + > + value = readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS); > + > + while (!(value & BIT(0)) && (value & BIT(2) || value & BIT(1))) { It would be useful to introduce some defines for these bits, so that we can reason about why bit 0 must always be set or neither bit 1 nor bit 2 can be, in order to consider this done > + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); This write may be left unobserved by the hardware for quite some time, but IIUC it's vital for the next write to make sense (i.e. you won't meet the delay below as they may be buffered and reach the endpoint essentially together) > + > + usleep_range(10, 20); https://www.kernel.org/doc/Documentation/timers/timers-howto.txt suggests this should be an udelay, so that we can accurately reach this (small) period > + > + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); If these writes aren't actually necessary to be repeated a 1000 times, you may want to use readl_poll_timeout Konrad > + > + value = readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS); > + if (++count >= 1000) { > + dev_err(core->dev, "LPI handshake timeout\n"); > + break; > + } > + } > + > ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS, > reg_val, reg_val & BIT(0), 200, 2000); > if (ret) > goto disable_power; > > - /* set MNoC to low power, set PD_NOC_QREQ (bit 0) */ > - writel(BIT(0), core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); > + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); > > writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, > core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); > > --- > base-commit: d968e50b5c26642754492dea23cbd3592bde62d8 > change-id: 20250812-sm8650-power-sequence-fix-ba9a92098233 > > Best regards,