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[87.95.85.22]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-553ac120167sm456434e87.20.2025.06.13.07.04.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Jun 2025 07:04:50 -0700 (PDT) Message-ID: <738a889d-9bd5-40c3-a8f5-f76fcde512f4@oss.qualcomm.com> Date: Fri, 13 Jun 2025 17:04:47 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 08/17] drm/msm/dsi/phy: Fix reading zero as PLL rates when unprepared To: Krzysztof Kozlowski Cc: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> <20250610-b4-sm8750-display-v6-8-ee633e3ddbff@linaro.org> Content-Language: en-US From: Dmitry Baryshkov In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjEzMDEwMyBTYWx0ZWRfX63EdUsVMSYbq LtByKYw3piT/Meh6Ug6m5gjThgf8a9n5GXrHPBALEAwKUbLbsUWLpggFIF6TdERRVKRn70B9MxL gFuHysAZAbLTjhLUxtOoZlpIdpwD+eq0z2pBc3ArVkVpbiU6eVY1ZJ8P5PME2rE4m87ZFewPVv9 FuDupwpqrVjMfYrWN/KFRkRml/SI+5YltsnYsIKgzLi1D2169d2dZoX1amnwvqt6F02+5hrHTP+ p0PXooi/vj1jV7TRPlxzx3h0ROEqtgZuAXridWJlgJzOhOYrKygKWkFFCqh+nnj4sLmXdhzXGf5 Rtoy4UVYz3gclhANB69xL+FPenqyzycjC0KHMso03/SukwwRm1GQl5ng1um0ID9wGQiDnXgvwxF Jle6x1uTp352eSUCEHB67XtDLo5ga2Uvw0L6oWolteUfvFiatYB0ZMIV8ZpE5k3CROzXfHIk X-Proofpoint-ORIG-GUID: isGFsXqTwVN57xl0BBJq_WatE-MxP8qn X-Proofpoint-GUID: isGFsXqTwVN57xl0BBJq_WatE-MxP8qn X-Authority-Analysis: v=2.4 cv=Jce8rVKV c=1 sm=1 tr=0 ts=684c301f cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=E+pfOR1jn8a0x6QusqFK4Q==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=0NLLj492lcDJW-k-HvMA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-13_01,2025-06-12_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 mlxlogscore=671 priorityscore=1501 malwarescore=0 spamscore=0 impostorscore=0 mlxscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506130103 On 13/06/2025 17:02, Krzysztof Kozlowski wrote: > On 13/06/2025 15:55, Dmitry Baryshkov wrote: >>> >>> @@ -361,24 +373,47 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll) >>> >>> static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll) >>> { >>> + unsigned long flags; >>> u32 data; >>> >>> + spin_lock_irqsave(&pll->pll_enable_lock, flags); >>> + --pll->pll_enable_cnt; >>> + if (pll->pll_enable_cnt < 0) { >>> + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); >>> + DRM_DEV_ERROR_RATELIMITED(&pll->phy->pdev->dev, >>> + "bug: imbalance in disabling PLL bias\n"); >>> + return; >>> + } else if (pll->pll_enable_cnt > 0) { >>> + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); >>> + return; >>> + } /* else: == 0 */ >>> + >>> data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); >>> data &= ~DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB; >>> writel(0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES); >>> writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); >>> + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); >>> ndelay(250); >> >> What is this ndelay protecting? Is is to let the hardware to wind down >> correctly? I'm worried about dsi_pll_disable_pll_bias() beng followed up >> by dsi_pll_enable_pll_bias() in another thread, which would mean that >> corresponding writes to the REG_DSI_7nm_PHY_CMN_CTRL_0 can come up >> without any delay between them. >> > > Great question, but why do you ask me? The code was there already and > MSM DRM drivers are not something I know and could provide context about. Because it's you who are changing the code as you've faced the issue with recalc_rate. > > > Best regards, > Krzysztof -- With best wishes Dmitry