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charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTA5MDA4NyBTYWx0ZWRfX4zzvydsRplEs pqJfMeMaWHQ8ZW70HNUbCjB8do/CShgETaiuOPns8KgolxJRVSgmMe+8Tfg2h4XGzs/z71xPryR WtCT2p2yG46G+abJcVHQSd8NfN6mgIvoE/oMm9ZKQ8wK099iPnnNDPP9/zXF9w8rta91P/4MSiU btRkG2cEM5df2FUO2pWTdxAsbMhuqqVX1iVyL4QdqY4WefvSd23HVFJNNP7oAhfDq/5ZXyOSUtg UP88r7Qj6jw7hUh+2S5465QDL+xCOUMRebizpbAzbBKPcVqodIBCy+pubx7glB4B4qwOxc/6AS8 KmON2hyMM6NtUrWtZGSbAa7e/hWL/lGSSOIbp5LtjMr47YsaHCqznKxLxiLoi5aHAv/v2z9DhvM h0SFCqUMK0yo3KO7gSgPaeT52OFR+lbg+EyqqswRTWfFeLak1wmTVt5PeXJjE7zB44EEm8Gt X-Authority-Analysis: v=2.4 cv=LKFmQIW9 c=1 sm=1 tr=0 ts=681dc54d cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=KtguLzq4JQKON55N9fIA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: rb27hl35HjopbzTLVNaDzE77O7gZnewt X-Proofpoint-GUID: rb27hl35HjopbzTLVNaDzE77O7gZnewt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-09_03,2025-05-08_04,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=841 clxscore=1015 lowpriorityscore=0 suspectscore=0 malwarescore=0 mlxscore=0 bulkscore=0 spamscore=0 phishscore=0 adultscore=0 priorityscore=1501 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505090087 On 5/3/2025 11:11 AM, Dmitry Baryshkov wrote: > On Tue, Apr 29, 2025 at 11:03:34PM +0530, Viken Dadhaniya wrote: >> Default pinctrl configurations for all QUP (Qualcomm Universal Peripheral) >> Serial Engines (SEs) are missing in the SoC device tree. These >> configurations are required by client teams when enabling any SEs as I2C, >> SPI, or Serial protocols. >> >> Add default pin configurations for Serial Engines (SEs) for all supported >> protocols, including I2C, SPI, and UART, to the sa8775p device tree. This >> change facilitates slave device driver clients to enable usecase with >> minimal modifications. >> >> Remove duplicate pin configurations from target-specific file as same pin >> configuration is included in the SoC device tree. >> >> Signed-off-by: Viken Dadhaniya >> --- >> v2 -> v3: >> >> - Remove duplicate pin configurations from target-specific file. >> >> v2 Link: https://lore.kernel.org/lkml/20250324151047.842648-1-quic_vdadhani@quicinc.com/ >> >> v1 -> v2: >> >> - Drop drive-strength and bias property from soc dtsi. >> - Update commit log. >> >> v1 Link: https://lore.kernel.org/lkml/20250225154136.3052757-1-quic_vdadhani@quicinc.com/ >> --- >> --- >> --- >> arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 35 - >> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 750 +++++++++++++++++++++ >> 2 files changed, 750 insertions(+), 35 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi >> index 967913169539..3b4243ef37e7 100644 >> --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi >> @@ -508,15 +508,11 @@ queue3 { >> >> &i2c11 { >> clock-frequency = <400000>; >> - pinctrl-0 = <&qup_i2c11_default>; >> - pinctrl-names = "default"; >> status = "okay"; >> }; >> >> &i2c18 { >> clock-frequency = <400000>; >> - pinctrl-0 = <&qup_i2c18_default>; >> - pinctrl-names = "default"; >> status = "okay"; >> }; >> >> @@ -678,8 +674,6 @@ &sleep_clk { >> }; >> >> &spi16 { >> - pinctrl-0 = <&qup_spi16_default>; >> - pinctrl-names = "default"; >> status = "okay"; >> }; >> >> @@ -712,80 +706,53 @@ ethernet0_mdio: ethernet0-mdio-pins { >> }; >> }; >> >> - qup_uart10_default: qup-uart10-state { >> - pins = "gpio46", "gpio47"; >> - function = "qup1_se3"; >> - }; >> - >> qup_spi16_default: qup-spi16-state { >> - pins = "gpio86", "gpio87", "gpio88", "gpio89"; >> - function = "qup2_se2"; >> drive-strength = <6>; >> bias-disable; >> }; > > If you are movign parts of these pinstates to the sa8775p.dtsi, then you > should also turn these declarations into label-based updates: > > &qup_spi16_default { > drive-strength = <6>; > bias-disable; > }; > > Otherwise the configuration is fragile: if the name gets changed, then > two parts will not match. > Sure, Updated in v4. >> >> qup_i2c11_default: qup-i2c11-state { >> - pins = "gpio48", "gpio49"; >> - function = "qup1_se4"; >> drive-strength = <2>; >> bias-pull-up; >> }; >> >> >