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Tue, 30 Dec 2025 02:57:38 -0800 (PST) Received: from [192.168.88.32] ([212.105.153.12]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-432613f7e6esm57485963f8f.21.2025.12.30.02.57.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 30 Dec 2025 02:57:38 -0800 (PST) Message-ID: <73f3d573-c093-469b-ac7e-36fdb7832933@redhat.com> Date: Tue, 30 Dec 2025 11:57:37 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net] net: dlink: mask rx_coalesce/rx_timeout before writing RxDMAIntCtrl To: Andrew Lunn , Yeounsu Moon Cc: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251223001006.17285-1-yyyynoom@gmail.com> Content-Language: en-US From: Paolo Abeni In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 12/23/25 10:43 AM, Andrew Lunn wrote: > On Tue, Dec 23, 2025 at 09:10:06AM +0900, Yeounsu Moon wrote: >> RxDMAIntCtrl encodes rx_coalesce in the low 16 bits >> and rx_timeout in the high 16 bits. If either value exceeds >> the field width, the current code may truncate the value and/or >> corrupt adjacent bits when programming the register. >> >> Mask both values to 16 bits and cast to u32 before shifting >> so only the intended fields are written. > > It would be better to do range checks in rio_probe1() and call > netdev_err() and return -EINVAL? > > Anybody trying to use very large values then gets an error message > rather than it working, but not as expected. I'm not sure we can do such change: any eventual user with bad setting will get a broken setup after kernel update. I think we should avoid such regression, and use something similar to this patch. @Yeounsu: the type cast in the current patch is not needed, please drop it, thanks! Paolo