mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
To: Marc Kleine-Budde <mkl@pengutronix.de>
Cc: Vincent Mailhol <mailhol@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Frank Li <Frank.Li@nxp.com>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	linux-can@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, imx@lists.linux.dev,
	linux-arm-kernel@lists.infradead.org,
	NXP S32 Linux Team <s32@nxp.com>,
	Christophe Lizzi <clizzi@redhat.com>,
	Alberto Ruiz <aruizrui@redhat.com>,
	Enric Balletbo <eballetb@redhat.com>,
	Eric Chanudet <echanude@redhat.com>
Subject: Re: [PATCH v2 0/5] can: flexcan: Add NXP S32N79 SoC support
Date: Thu, 19 Mar 2026 16:14:46 +0200	[thread overview]
Message-ID: <742c748b-8096-49a3-b1a4-3a8507f6f55d@oss.nxp.com> (raw)
In-Reply-To: <20260319-orca-of-legal-science-88e67d-mkl@pengutronix.de>

On 3/19/2026 1:56 PM, Marc Kleine-Budde wrote:
> On 19.03.2026 10:40:27, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>
>> This patch series adds FlexCAN support for the NXP S32N79 SoC.
>>
>> The S32N79 is an automotive-grade processor from NXP with multiple
>> FlexCAN instances. The FlexCAN IP integration on S32N79 differs from
>> other SoCs in the interrupt routing - it uses two separate interrupt
>> lines:
>>    - one interrupt for mailboxes 0-127
>>    - one interrupt for bus error detection and device state changes
>>
>> The CAN controllers are connected through an irqsteer interrupt
>> controller in the RCU (Resource Control Unit) domain.
>>
>> This series:
>>    1. Adds dt-bindings documentation for S32N79 FlexCAN
>>    2. Introduces FLEXCAN_QUIRK_IRQ_BERR to handle the two-interrupt
>>       configuration
>>    3. Adds S32N79 device data and compatible string to the driver
>>    4. Adds FlexCAN device tree nodes for S32N79 SoC
>>    5. Enables FlexCAN devices on the S32N79-RDB board
>>
>> Tested on S32N79-RDB board with CAN and CAN FD communication.
> 
> I think DTS changes go into a separate series.
> 

Hi Marc,

I added the devicetree list to this thread.

> Please also have a look at the AI review:
> 
> https://sashiko.dev/#/patchset/20260318092215.23505-1-ciprianmarian.costea%40oss.nxp.com
> 
> Especially on patch#3.
> 
> I think we should split the main IRQ handler into 3 parts, message buff,
> bus error and state change.
> 
> regards,
> Marc
> 

Thanks for pointing to the AI review.

It raises two concerns:

1. Duplicate event processing (can be addressed by splitting the handler
as you've suggested).

This is a pre-existing issue affecting S32G2 (NR_IRQ_3 with 4 IRQ lines
to the same handler) and MCF5441X (3 IRQ lines on the same handler).
I'll include this as a preparatory patch in the next version of the series.

2. Concurrent skb_irq_queue access (pre-existing, separate scope)

The __skb_queue_add_sort() calls on offload->skb_irq_queue are lockless.
When the mb and esr handlers run concurrently on different CPUs, both
can manipulate the list simultaneously.
This is a valid concern, but it's also pre-existing.

The fix requires changes in CAN core's rx-offload.c rather than in
flexcan, so I think it would be better handled in a separate series.

Would you agree ?

Best regards,
Ciprian



  reply	other threads:[~2026-03-19 14:14 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-19  9:40 Ciprian Costea
2026-03-19  9:40 ` [PATCH v2 1/5] dt-bindings: can: fsl,flexcan: add " Ciprian Costea
2026-03-19  9:40 ` [PATCH v2 2/5] can: flexcan: add FLEXCAN_QUIRK_IRQ_BERR quirk Ciprian Costea
2026-03-19  9:40 ` [PATCH v2 3/5] can: flexcan: add NXP S32N79 SoC support Ciprian Costea
2026-03-19 10:54   ` Marc Kleine-Budde
2026-03-19 11:24     ` Ciprian Marian Costea
2026-03-19  9:40 ` [PATCH v2 4/5] arm64: dts: s32n79: add FlexCAN nodes Ciprian Costea
2026-03-19  9:40 ` [PATCH v2 5/5] arm64: dts: s32n79: enable FlexCAN devices Ciprian Costea
2026-03-19 11:56 ` [PATCH v2 0/5] can: flexcan: Add NXP S32N79 SoC support Marc Kleine-Budde
2026-03-19 14:14   ` Ciprian Marian Costea [this message]
2026-03-19 14:42     ` Marc Kleine-Budde

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=742c748b-8096-49a3-b1a4-3a8507f6f55d@oss.nxp.com \
    --to=ciprianmarian.costea@oss.nxp.com \
    --cc=Frank.Li@nxp.com \
    --cc=aruizrui@redhat.com \
    --cc=clizzi@redhat.com \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=eballetb@redhat.com \
    --cc=echanude@redhat.com \
    --cc=festevam@gmail.com \
    --cc=imx@lists.linux.dev \
    --cc=kernel@pengutronix.de \
    --cc=krzk+dt@kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-can@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mailhol@kernel.org \
    --cc=mkl@pengutronix.de \
    --cc=robh@kernel.org \
    --cc=s.hauer@pengutronix.de \
    --cc=s32@nxp.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®